IDT7187L Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT7187L Datasheet PDF : 8 Pages
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IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1,2,3,4)
tWC
ADDRESS
tAW
CS
t AS
tWP
t WR
WE
DATA OUT
DATA IN
t WZ (5)
tOW (5)
t DW
t DH
VALID DATA
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
2986 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1,2,4)
t WC
ADDRESS
tAW
CS
tAS
WE
(3)
tCW
tWR
t DW
t DH
DATA IN
VALID DATA
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
2986 drw 10
6.2
7
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