ADA4084-1ARJZ-RL Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADA4084-1ARJZ-RL

30 V, Low Noise, Rail-to-Rail Input/Output, Low Power Operational Amplifiers

Analog Devices 

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Supply Voltage

Input Voltage

Differential Input Voltage1

Output Short-Circuit Duration to GND

Storage Temperature Range

Operating Temperature Range

Junction Temperature Range

Lead Temperature (Soldering 60 sec)

ESD

Human Body Model2

Machine Model3

Field-Induced Charged-Device Model

(FICDM)4

Rating

±18 V

V− ≤ VIN ≤ V+

±0.6 V

Indefinite

−65°C to +150°C

−40°C to +125°C

−65°C to +150°C

300°C

4.5 kV

200 V

1.25 kV

1 For input differential voltages greater than 0.6 V, limit the input current to

less than 5 mA to prevent degradation or destruction of the input devices.

2 Applicable standard: MIL-STD-883, Method 3015.7.

3 Applicable standard: JESD22-A115-A (ESD machine model standard of

JEDEC).

4 Applicable standard: JESD22-C101-C (ESD FICDM standard of JEDEC).

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ADA4084-1/ADA4084-2/ADA4084-4

THERMAL RESISTANCE

θJA is specified for the device soldered on a 4-layer JEDEC

standard printed circuit board (PCB) with zero airflow.

Table 6. Thermal Resistance

Package Type

5-Lead SOT-23 (RJ-5)

8-Lead SOIC_N (R-8)

8-Lead MSOP (RM-8)

8-Lead LFCSP (CP-8-11)1, 3

14-Lead TSSOP (RU-14)

16-Lead LFCSP (CP-16-17)2, 3

θJA

219.4

121

142

84

112

55

θJC

155.6

43

45

40

43

30

Unit

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

1 Values are based on 4-layer (2S2P) JEDEC standard PCB, with four thermal

vias. Exposed pad soldered to PCB.

2 Values are based on 4-layer (2S2P) JEDEC standard PCB, with nine thermal

vias. Exposed pad soldered to PCB.

3 θJC measured on top of package.

ESD CAUTION

R4

R3

VCC

R6

Q24 Q23

D2

D1

Q1

Q2

D100

Q4

D101

Q3

FOLDED

CASCADE

MIRROR

VOUT

D5

R1

R2

Q13

R7 C2

D4

VBIAS

Q18

R5

C1

Q21

D20

Figure 2. Simplified Schematic

Q19

VEE

Rev. I | Page 7 of 36

Share Link: