74LVC273D Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LVC273D Datasheet PDF : 17 Pages
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Nexperia
74LVC273
Octal D-type flip-flop with reset; positive-edge trigger
VI
MR input
GND
VI
CP input
GND
VOH
Qn output
VOL
VM
tW
trec
tPHL
VM
VM
mna464
Fig 6.
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Master reset (MR) pulse width, the master reset to output (Qn) propagation delays, and the master reset
to clock (CP) recovery time
VI
CP input
GND
VI
Dn input
GND
VM
t su
th
VM
t su
th
VOH
Qn output
VOL
VM
mna767
Fig 7.
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Data set-up and hold times for the data input (Dn)
74LVC273
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 31 December 2012
© Nexperia B.V. 2017. All rights reserved
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