74LVC273PW Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LVC273PW Datasheet PDF : 17 Pages
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Nexperia
74LVC273
Octal D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
MR 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
273
15 Q5
14 D5
13 D4
12 Q4
11 CP
001aad093
Fig 3. Pin configuration for SO20 and (T)SSOP20
terminal 1
index area
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
273
GND(1)
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
001aad094
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
MR
CP
D[0:7]
Q[0:7]
GND
VCC
Pin description
Pin
1
11
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
10
20
Description
master reset input (active LOW)
clock input (LOW-to-HIGH; edge-triggered)
data input
flip-flop output
ground (0 V)
supply voltage
74LVC273
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 31 December 2012
© Nexperia B.V. 2017. All rights reserved
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