CXD2548 Ver la hoja de datos (PDF) - Sony Semiconductor
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CXD2548 Datasheet PDF : 113 Pages
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CXD2548R
(2) CLOK, DATA, XLAT, SQCK, and EXCK pins
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Clock frequency
fCK
Clock pulse width
tWCK
Setup time
tSU
Hold time
tH
Delay time
tD
Latch pulse width
tWL
EXCK, SQCK frequency fT
EXCK, SQCK pulse width fWT
Min.
750
300
300
300
750
750∗1
Typ.
Max.
0.65
0.65∗1
Unit
MHz
ns
ns
ns
ns
ns
MHz
ns
CLK
1/fCK
tWCK
tWCK
DATA
XLT
tSU tH
tD
tWL
EXCK
SQCK
tWT
tWT
1/fT
SUBQ
SQCK
tSU tH
∗1 In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCL maximum operating
frequency is 300kHz and its minimum pulse width is 1.5µs.
(3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
BCK pulse width
DATAL, R setup time
DATAL, R hold time
LRCK setup time
Symbol Conditions Min.
tW
94
tSU
18
tH
18
tSU
18
Typ.
Max. Unit
ns
ns
ns
ns
tW(BCKI) tW(BCKI)
BCKI
VDD/2
VDD/2
tSU
tH
(PCMDI) (PCMDI)
PCMDI
tSU
(LRCKI)
LRCKI
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