CXD2507AQ Ver la hoja de datos (PDF) - Sony Semiconductor
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CXD2507AQ Datasheet PDF : 38 Pages
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CXD2507AQ
2) CLOK, DATA, XLAT, CNIN, SQCK EXCK pins
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol Min.
Typ. Max. Unit
Clock frequency
fCK
Clock pulse width
tWCK
Setup time
tSU
Hold time
tH
Delay time
tD
Latch pulse width
tWL
EXCK SQCK frequency fT
EXCK SQCK pulse width tWT
750
300
300
300
750
750∗
0.65
0.65∗
MHz
ns
ns
ns
ns
ns
MHz
ns
CLK
1/fCX
tWCK
tWCK
DATA
XLT
EXCK
CNIN
SQCK
SBSO
SQSO
tSU tH
tWT
tWT
1/fr
tSU tH
tD
tWL
∗ In low power consumption and special playback mode, when SL0 = SL1 = 1, the maximum operating
frequency for SQCK is 300kHz and the minimum pulse width is 1.5µs.
Description of Functions
1. CPU Interface and Instructions
• CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.
750ns or more
CLOK
DATA
XLAT
D1 D2 D3 D0 D1 D2 D3
Data
Address
750ns or more
Registers 4 to E
Valid
300ns max
• Information on each address and the data is provided in Table 1-1.
• The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2.
Note) When XLAT is low, EXCK and SQCK must be set high.
–8–
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