CXD2507AQ Ver la hoja de datos (PDF) - Sony Semiconductor
Número de pieza
componentes Descripción
Fabricante
CXD2507AQ Datasheet PDF : 38 Pages
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CXD2507AQ
Pin
No.
Symbol
I/O
Description
37 FSTT O 1, 0
38 C4M O 1, 0
39 DOUT O 1, 0
40 EMPH O 1, 0
41 WFCK O 1, 0
42 VSS
——
43 SCOR O 1, 0
44 SBSO O 1, 0
45 EXCK I
46 SQSO O 1, 0
47 SQCK I
48 MUTE I
49 SENS O 1, 0
50 XRST I
51 DATA I
52 XLAT I
53 CLOK I
54 SEIN I
55 CNIN I
56 DATO O 1, 0
57 XLTO O 1, 0
58 VDD
——
59 CLKO O 1, 0
60 SPOA I
61 SPOB I
62 SPOC I
63 SPOD I
64 XLON O 1, 0
2/3 frequency divider output for Pins 34 and 35.
4.2336MHz output.
Digital Out output.
Outputs high signal when the playback disc has emphasis, low signal when no emphasis.
WFCK output.
GND.
Outputs high signal when either subcode sync S0 or S1 is detected.
Sub P to W serial output.
SBSO readout clock input.
SubQ 80-bit serial output.
SQSO readout clock input.
High: mute; low: release
SENS output to CPU.
System reset. Reset when low.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
Sense input from SSP.
Track jump count signal input.
Serial data output to SSP.
Serial data latch output to SSP. Latched at the falling edge.
Power supply (+5V).
Serial data transfer clock output to SSP.
Microcomputer extended interface (input A).
Microcomputer extended interface (input B).
Microcomputer extended interface (input C).
Microcomputer extended interface (input D).
Microcomputer extended interface (output).
Notes)
• PCMD is two's complement output of MSB first.
• GTOP is used to monitor the frame sync protection status.
• XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before
sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy. This signal has a cycle of 136µ.
• C2PO represents the data error status.
• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
–5–
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