CXD3605R Ver la hoja de datos (PDF) - Sony Semiconductor
Número de pieza
componentes Descripción
Fabricante
CXD3605R Datasheet PDF : 36 Pages
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CXD3605R
Pin Description
Pin
No.
Symbol
I/O
Description
1 VSS1
— GND
2 RST
I
Internal system reset input.
Normally apply reset during power-on.
High: Normal operation, Low: Reset control
Schmitt trigger input
3
SNCSL
I
Control input used to switch sync system. High: CKI sync, Low: MCKO sync
With pull-down resistor
4
ID/EXP
O
Vertical direction line identification pulse output/exposure time identification pulse
output. Switching possible using the serial interface data. (Default: ID)
5 WEN
O Memory write timing pulse output.
6 SSGSL I Internal SSG enable.
High: Internal SSG valid, Low: External sync valid.
With pull-down resistor
7 VDD1
— 3.3V power supply. (Power supply for common logic block)
8 VDD2
— 3.3V power supply. (Power supply for RG)
9 RG
O CCD reset gate pulse output.
10 VSS2
— GND
11 VSS3
— GND
12 H1
O CCD horizontal register clock output.
13 H2
O CCD horizontal register clock output.
14 VDD3
— 3.3 to 5.0V power supply. (Power supply for H1/H2)
15 VDD4
— 3.3V power supply. (Power supply for CDS block)
16 XSHP O CCD precharge level sample-and-hold pulse output.
17 XSHD O CCD data level sample-and-hold pulse output.
18 XRS
O Sample-and-hold pulse output for analog/digital conversion phase alignment.
19 PBLK O Pulse output for horizontal and vertical blanking period pulse cleaning.
20 CLPDM O CCD dummy signal clamp pulse output.
21 VSS4
— GND
22
OBCLP
O
CCD optical black signal clamp pulse output.
The horizontal/vertical OB pattern can be changed using the serial interface data.
23
ADCLK
O
Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.
24 VSS5
— GND
25 CKO
O Inverter output.
26 CKI
I Inverter input.
27 OSCO O Inverter output for oscillation.
When not used, leave open or connect a capacitor.
28 OSCI
I Inverter input for oscillation.
When not used, fix low.
29 VDD5
— 3.3V power supply. (Power supply for common logic block)
30 MCKO O System clock output for signal processing IC.
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