CXD3605R Ver la hoja de datos (PDF) - Sony Semiconductor
Número de pieza
componentes Descripción
Fabricante
CXD3605R Datasheet PDF : 36 Pages
| |||
CXD3605R
Serial interface clock internal loading characteristics (2)
VD
HD
Enlarged view
Example: During frame mode
VD
0.2VDDd
HD
SEN
ts1
0.8VDDd
th1
0.2VDDd
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VD.
Symbol
ts1
th1
(Within the recommended operating conditions)
Definition
SEN setup time, activated by the falling edge of VD
SEN hold time, activated by the falling edge of VD
Min. Typ. Max. Unit
0
ns
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3605R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3605R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
Output signal
0.8VDDd
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
tpdPULSE Output signal delay, activated by the rising edge of SEN
Min. Typ. Max. Unit
5
100 ns
– 10 –
Share Link: 