CMX654 Ver la hoja de datos (PDF) - CML Microcircuits
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CMX654 Datasheet PDF : 13 Pages
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V.23 Transmit Modulator
CMX654
CMX654
D4/P3
Signal
Description
Pin No.
Name
Type
9
VBIAS
O/P Internally generated bias voltage, held at VDD/2
when the device is not in 'Zero-Power' mode.
Should be decoupled to VSS by a capacitor
mounted close to the device pins.
10
-
-
Connect to VDD.
11
TXD
I/P A logic level input for either the raw input to the
FSK Modulator or data to be re-timed depending
on the state of the M0, M1 and CLK inputs. See
Section 1.5.3.
12
CLK
I/P A logic level input which may be used to clock
data bits into the Tx FSK Data Retiming block.
13
-
N/C No connection, do not connect to this pin.
14
-
N/C No connection, do not connect to this pin.
15
RDYN
O/P "Ready for Tx data transfer" output of the on-
chip data retiming circuit. This open-drain active
low output may be used as an Interrupt
Request/Wake-up input to the associated µC. An
external pull-up resistor should be connected
between this output and VDD.
16
VDD
Power The positive supply rail. Levels and thresholds
within the device are proportional to this voltage.
Should be decoupled to VSS by a capacitor
mounted close to the device pins.
Notes: I/P = Input
O/P = Output
N/C = No Connection
VDD and VBIAS decoupling are very important. It is recommended that the decoupling capacitors are placed so
that connections between them and the device pins are as short as practicable.
© 1998 Consumer Microcircuits Limited
4
D/654/3
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