CD4017BMS Ver la hoja de datos (PDF) - Renesas Electronics

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componentes Descripción

Fabricante

CD4017BMS

CMOS Counter/Dividers

Renesas Electronics 

CD4017BMS, CD4022BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC

700

600

500

400

SUPPLY VOLTAGE (VDD) = 5V

300

10V

200

100

15V

0 10 20 30 40 50 60 70 80 90 100

LOAD CAPACITANCE (CL) (pF)

FIGURE 11. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

(CLOCK TO CARRY OUT)

CLOCK

TS

CLOCK

INHIBIT

RESET

DECODE

1-9

OUTPUT

TPLH

TPHL

TPRHL

DECODE

“0” OR

CARRY

OUTPUT

TPHL

TPRLH

Delays Measured Between 50% levels on All Waveforms

FIGURE 13. PROPAGATION DELAY, SETUP, AND RESET

REMOVAL TIME WAVEFORMS

105 LOAD CAPACITANCE

CL = 50pF

CL = 15pF

104

SUPPLY VOLTAGE

(VDD) = 15V

103

10V

10V

5V

102

10

1

AMBIENT TEMPERATURE (TA) = +25oC

INPUT tr = tf = 20ns

10

102

103

104

105

CLOCK INPUT FREQUENCY (fCL) (kHz)

FIGURE 12. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF CLOCK INPUT FREQUENCY

CLOCK

CLOCK

INHIBIT

CD4017BMS

OR

CD4022BMS

0 1 2 ...

N

N DECODED O DECODED

OUTPUTS OUTPUTS

COUT FOR N  6

f = CLOCKN

ALTERNATE COUT

FOR N = 2 TO 10

f = CLOCKN

FIGURE 14. DIVIDE BY N COUNTER (N  10) WITH N DECODED

OUTPUTS

C

R

CE CD4017BMS

Q0 Q1 . . . Q8 Q9

C

R

CE CD4017BMS

Q0 Q1 . . . Q8 Q9

C

R

CE CD4017BMS

Q0 Q1 . . . Q8 Q9

9 DECODED

OUTPUTS

8 DECODED

OUTPUTS

8 DECODED

OUTPUTS

CLOCK

FIRST STAGE

INTERMEDIATE STAGE

LAST STAGE

FIGURE 15. CASCADING THE CD4017BMS

When the Nth decoded output is reached (Nth clock pulse) the S-

R flip-flop (constructed from two NOR gates of the CD4001B)

generates a reset pulse which clears the CD4017BMS or

CD4022BMS to its zero count. At this time, if the Nth decoded out-

put is greater than or equal to 6 in the CD4017BMS or 5 in the

CD4022BMS, the COUT line goes high to clock the next

CD4017BMS or CD4022BMS counter section. The “0” decoded

output also goes high at this time. Coincidence of the clock low

and decoded “0” output low resets the S-R flip-flop to enable the

CD4017BMS or CD4022BMS. If the Nth decoded output is less

than 6 (CD4017BMS) or 5 (CD4022BMS), the COUT line will not

go high and, therefore, cannot be used. In this case “0” decoded

output may be used to perform the clocking function for the next

counter.

FN3297 Rev 0.00

August 1998

Page 9 of 10

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