MAX706ATEPA Ver la hoja de datos (PDF) - Maxim Integrated
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MAX706ATEPA Datasheet PDF : 15 Pages
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+3V Voltage Monitoring, Low-Cost µP
Supervisory Circuits
Pin Description
PIN
MAX706P
MAX706AP
MAX706R/S/T,
MAX706AR/AS/AT
MAX708R/S/T
NAME
FUNCTION
SO/DIP µMAX SO/DIP µMAX SO/DIP µMAX
Active-Low, Manual-Reset Input. Pull MR below 0.6V to trigger a
1
3
1
3
1
3
MR
reset pulse. MR is TTL/CMOS compatible when VCC = 5V and can
be shorted to GND with a switch. MR is internally connected to a
70µA source current. Connect to VCC or leave unconnected.
2
4
2
4
2
4
VCC Supply Voltage Input
3
5
3
5
3
5 GND Ground
Adjustable Power-Fail Comparator Input. Connect PFI to a
4
6
4
6
4
6
PFI
resistive divider to set the desired PFI threshold. When PFI is
less than 1.25V, PFO goes low and sinks current; otherwise,
PFO remains high. Connect PFI to GND if not used.
Active-Low, Power-Fail Comparator Output. PFO asserts when
5
7
5
7
5
7
PFO
PFI is below the internal 1.25V threshold. PFO deasserts when
PFI is above the internal 1.25V threshold. Leave PFO
unconnected if not used.
Watchdog Input. A falling or rising transition must occur at
WDI within 1.6s to prevent WDO from asserting (see Figure 4).
The internal watchdog timer is reset to zero when reset is
asserted or when transition occurs at WDI. The watchdog
6
8
6
8
—
— WDI function for the MAX706P/R/S/T can not be disabled. The
watchdog timer for the MAX706AP/AR/AS/AT disables when
WDI input is left open or connected to a tri-state output in its
high-impedance state with a leakage current of less than
600nA.
Active-High Reset Output. Reset remains high when VCC is
7
1
—
—
8
2 RESET below the reset threshold or MR is held low. It remains low for
200ms after the reset conditions end (Figure 3).
Active-Low Watchdog Output. WDO goes low when a
transition does not occur at WDI within 1.6s and remains low
until a transition occurs at WDI (indicating the watchdog
8
2
8
2
—
— WDO interrupt has been serviced). WDO also goes low when VCC
falls below the reset threshold; however, unlike the reset
output signal, WDO goes high as soon as VCC rises above
the reset threshold.
—
—
7
Active-Low Reset Output. RESET remains low when VCC is
1
7
1 RESET below the reset threshold or MR is held low. It remains low for
200ms after the reset conditions end (Figure 3).
—
—
—
—
6
8
N.C. No Connection. Not internally connected.
6 _______________________________________________________________________________________
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