IDT74FCT3932-100 Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT74FCT3932-100

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

Integrated Device Technology 

IDT74FCT3932-100, IDT74FCT32932-100

LOW SKEW PLL-BASED CMOS CLOCK DRIVER

COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE(7)

Symbol

tPD(3)

REF_IN-Q_FB

Parameter

Propagation Delay

(REF_IN input to Q outputs)

Condition(1)

No Load

Min.(2)

–0.5

tRISE/FALL

Rise/Fall Time (between 0.8 and 2.0V)

FCT3932 CL = 20pF for FCT3932 0.5

All Outputs

FCT32932 CL = 10pF for FCT32932 0.5

tPW(3)

Output Duty Cycle

45

tSKEWr(3,4)

Output to Output Skew (All outputs at

—

same frequency rising edge)

tSKEWf(3,4)

Output to Output Skew (All outputs at

—

same frequency falling edge)

tSKEWall(3,4)

Output to Output Skew (All outputs,

—

rising edge any frequency)

tLOCK (5)

Time required to acquire

1

Phase-Lock from time

REF_IN input signal is received

tPZH

Output Enable Time OEx

3.0

tPZL

(LOW-to-HIGH) to Q

tPHZ

Output Disable Time OEx

3.0

tPLZ

(HIGH-to-LOW) to Q

GENERAL AC SPECIFICATION NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested.

3. These specifications are guaranteed but not production tested.

4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.

5. With VCC fully powered-on and Q_FB properly connected to the FEEDBACK pin.

6. The tPD spec gives the limits of the phase offset between the REF_IN input and the Q_FB output.

7. The AC specifications are only guaranteed with the decoupling scheme shown in figure 2.

Max. Unit

+0.5 ns

1.5 ns

2.0

55 %

500 ps

500 ps

1.0 ns

10 ms

8.0 ns

8.0 ns

3267 tbl 13

tPD = ±0.5ns

REF_IN input

Offset

Feedback Output

3267 drw 03

9.9

6

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