IDT74FCT3932-100 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT74FCT3932-100 Datasheet PDF : 9 Pages
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IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Name
I/O
REF_IN
I
FEEDBACK
I
Q41-4
O
Q81-8
O
Q51-5
O
OE1-3
I
CNTRL1-4
I
Q_FB
O
RST
I
PLL_EN
I
LOCK
O
Description
Reference clock input.
Feedback input to phase detector.
BANK1 clock outputs.
BANK2 clock outputs.
BANK3 clock outputs.
Output enable controls for BANKS 1, 2 and 3 (Active LOW).
Control lines to select output configuration (see table).
Dedicated PLL feedback output.
Asynchronous reset (Active LOW).
Disables phase-lock for low frequency testing (Refer to functional block diagram).
PLL "LOCK" indicator (HIGH when PLL is locked).
3267 tbl 03
OUTPUT FREQUENCY CONFIGURATION AND INPUT FREQUENCY RANGE TABLE
MODE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CNTRL
4321
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
Q_FEEDBACK
F (divide-by-1)
F (divide-by-1)
F (divide-by-1)
F (divide-by-1)
F (divide-by-1)
F (divide-by-3)
F (divide-by-3)
F (divide-by-3)
F (divide-by-2)
F (divide-by-2)
F (divide-by-2)
F (divide-by-2)
F (divide-by-2)
F (divide-by-4)
F (divide-by-4)
F (divide-by-4)
Q_BANK1
(4 outputs)
F
F
F
F
F
3F
3F
3F
2F
2F
2F
2F
2F
4F
4F
4F
Q_BANK2
(8 outputs)
F
F
F
F/2
F/3
3F
F
3F
2F
F
F
F
F/2
2F
2F
2F
Q_BANK3
(5 outputs)
F
F/2
F
F/2
F
F
3F
3F
2F
2F
F
F/2
F
4F
2F
F
FIN Range
50-100MHz
50-100MHz
50-100MHz
50-100MHz
50-100MHz
16.7-33.3MHz
16.7-33.3MHz
16.7-33.3MHz
25-50MHz
25-50MHz
25-50MHz
25-50MHz
25-50MHz
12.5-25MHz
12.5-25MHz
12.5-25MHz
3267 tbl 04
9.9
3
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