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IDT74FCT3932-100

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

Integrated Device Technology 

IDT74FCT3932-100, IDT74FCT32932-100

LOW SKEW PLL-BASED CMOS CLOCK DRIVER

PIN CONFIGURATIONS

VCC

Q55

CNTRL1

GND

CNTRL2

CNTRL3

VCC

CNTRL4

Q_FB

FEEDBACK

GND

REF_IN

AVCC

NC

AGND

GND

OE1

OE2

OE3

RST

GND

PLL_EN

LOCK

VCC

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12 SO48-1 37

SO48-2

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

Q54

Q53

GND

Q52

Q51

VCC

Q44

Q43

GND

Q42

Q41

VCC

VCC

Q88

Q87

GND

Q86

Q85

VCC

Q84

Q83

GND

Q82

Q81

SSOP

TSSOP

TOP VIEW

3267 drw 02

*NC = No connect

COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

Symbol

Description

VTERM(2) Terminal Voltage with Respect to

GND

VTERM(3) Terminal Voltage with Respect to

GND

VTERM(4) Terminal Voltage with Respect to

GND

TSTG Storage Temperature

Max.

–0.5 to +4.6

–0.5 to +7.0

–0.5 to VCC

+ 0.5

–65 to +150

Unit

V

V

V

°C

IOUT

DC Output Current

–60 to +60 mA

NOTES:

3267 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect reliability.

2. Vcc terminals.

3. Input terminals.

4. Output and I/O terminals.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter(1) Conditions Typ. Max. Unit

CIN

Input

VIN = 0V

3.2 5.0 pF

Capacitance

CI/O

I/O

VOUT = 0V 3.7 8.0 pF

Capacitance

NOTE:

3267 lnk 02

1. This parameter is measured at characterization but not tested.

9.9

2

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