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M34C02-RMB6

2 Kbit serial I²C bus EEPROM for DIMM serial presence detect

STMicroelectronics 

Description

1

Description

M34C02-R

The M34C02-R is a 2 Kbit serial EEPROM memories able to lock permanently the data in its

first half (from location 00h to 7Fh). This facility has been designed specifically for use in

DRAM DIMMs (dual interline memory modules) with serial presence detect. All the

information concerning the DRAM module configuration (such as its access speed, its size,

its organization) can be kept write protected in the first half of the memory.

This bottom half of the memory area can be write-protected using a specially designed

software write protection mechanism. By sending the device a specific sequence, the first

128 Bytes of the memory become permanently write protected. Care must be taken when

using this sequence as its effect cannot be reversed. In addition, the device allows the entire

memory area to be write protected, using the WC input (for example by tieing this input to

t(s) VCC).

These I2C-compatible electrically erasable programmable memory (EEPROM) devices are

c organized as 256 × 8 bits.

du I2C uses a two wire serial interface, comprising a bidirectional data line and a clock line. The

ro ) device carries a built-in 4-bit device type identifier code (1010) in accordance with the I2C

P t(s bus definition to access the memory area and a second device type identifier code (0110) to

te c access the Protection Register. These codes are used together with three chip enable

le u inputs (E2, E1, E0) so that up to eight 2Kbit devices may be attached to the I²C bus and

d selected individually.

bso Pro The device behaves as a slave device in the I2C protocol, with all memory operations

synchronized by the serial clock. Read and Write operations are initiated by a Start

- O te condition, generated by the bus master. The Start condition is followed by a device select

) le code and RW bit (as described in Table 2), terminated by an acknowledge bit.

t(s so When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit

c b time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

u O bus master acknowledges the receipt of the data byte in the same way. Data transfers are

d - terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Pro t(s) Figure 1. Logic diagram

lete uc VCC

so rod 3

b P E0-E2

O lete SCL

Obso WC

M34C02-R

SDA

VSS

AI01931c

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