MAX5541(1999) Ver la hoja de datos (PDF) - Maxim Integrated
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MAX5541 Datasheet PDF : 8 Pages
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Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%, VREF = +2.5V, VAGND = VDGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DAC Glitch Impulse
Major-carry transition
10
nVs
Digital Feedthrough
Code = 0000 hex, CS = VDD,
SCLK = VDIN = 0 to VDD levels
10
nVs
DYNAMIC PERFORMANCE—REFERENCE SECTION
Reference -3dB Bandwidth
BW Code = FFFF hex
1
MHz
Reference Feedthrough
Code = 0000 hex, VREF = 1Vp-p at 100kHz
1
mVp-p
Signal-to-Noise Ratio
SNR
92
dB
Reference Input Capacitance
Code = 0000 hex
CIN
Code = FFFF hex
75
pF
120
STATIC PERFORMANCE—DIGITAL INPUTS
Input High Voltage
VIH
2.4
V
Input Low Voltage
VIL
0.8
V
Input Current
IIN
VIN = 0
±1
µA
Input Capacitance
CIN (Note 6)
10
pF
Hysteresis Voltage
VH
POWER SUPPLY
0.40
V
Positive Supply Range
VDD
4.75
5.25
V
Positive Supply Current
IDD
0.3
1.1
mA
Power Dissipation
PD
1.5
mW
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VREF = +2.5V, VAGND = VDGND = 0, CMOS inputs, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
SCLK Frequency
fCLK
SCLK Pulse Width High
tCH
45
SCLK Pulse Width Low
tCL
45
CS Low to SCLK High Setup
tCSS0
45
CS High to SCLK High Setup
tCSS1
45
SCLK High to CS Low Hold
tCSH0 (Note 6)
30
SCLK High to CS High Hold
tCSH1
45
DIN to SCLK High Setup
tDS
40
DIN to SCLK High Hold
tDH
VDD High to CS Low
(power-up delay)
0
20
MAX
10
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
µs
Note 1: Gain Error tested at VREF = +2.0V, +2.5V, and +3.0V.
Note 2: ROUT tolerance is typically ±20%.
Note 3: Min/Max ranges guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code dependent, minimum at 8555 hex.
Note 5: Slew-rate value is measured from 0% to 63%.
Note 6: Guaranteed by design. Not production tested.
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