ADNS-2030 Ver la hoja de datos (PDF) - Avago Technologies
Número de pieza
componentes Descripción
Fabricante
ADNS-2030 Datasheet PDF : 34 Pages
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Recommended Operating Conditions
Parameter
Symbol Minimum Typical Maximum Units
Notes
Operating Temperature
TA
0
40
°C
Power Supply Voltage
VDD
3.0
3.3
3.6
Volts
Power Supply Rise Time
VRT
100
ms
Supply Noise
VN
30
mV
Peak to peak @27 MHz bandwidth
Clock Frequency
fCLK
17.4
18.0
18.7
MHz
Set by ceramic resonator
Serial Port Clock Frequency
SCLK
fCLK/4
MHz
Resonator Impedance
XRES
55
Ω
Distance from Lens Reference Z
2.3
2.4
2.5
mm
Plane to Surface
Results in ±0.2 mm DOF
(See Figure 9.)
Speed
S
0
14
in/sec
@ frame rate = 1500 fps
Acceleration
A
0.15
g
@ frame rate = 1500 fps
Light Level onto IC
IRRINC
80
100
25,000
mW/m2
30,000
λ = 639 nm
λ = 875 nm
SDIO Read Hold Time
tHOLD
100
µs
Hold time for valid data
(Refer to Figure 27.)
SDIO Serial Write-write Time
tSWW
100
µs
Time between two write commands
(Refer to Figure 30.)
SDIO Serial Write-read Time
tSWR
100
µs
Time between write and read
operation (Refer to Figure 31.)
SDIO Serial Read-write Time
tSRW
120
ns
Time between read and write
operation (Refer to Figure 32.)
SDIO Serial Read-read Time
tSRR
120
ns
Time between two read commands
(Refer to Figure 32.)
Data Delay after PD ↓
tCOMPUTE
3.2
ms
After tCOMPUTE, all registers contain
data from first image after PD ↓.
Note that an additional 75 frames
for AGC stabilization may be required
if mouse movement occurred while
PD was high. (Refer to Figure 11.)
SDIO Write Setup Time
tSETUP
60
ns
Data valid time before the rising of
SCLK (Refer to Figure 25.)
PD Pulse Width
tPDW
700
µs
(to power down the chip)
Pulse width to initiate the power down
cycle @1500 fps (Refer to Figure 13.)
PD Pulse Width
tPD
100
µs
(to reset the serial port)
Pulse width to reset the serial port
@1500 fps (but may also initiate a
power down cycle) (Refer to Figure 11.)
Frame Rate
FR
1500
frames/s See Frame_Period register section
Bin Resistor
R1
15K
15K
37K
Ω
Refer to Figure 8
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