MAX703 Ver la hoja de datos (PDF) - Maxim Integrated
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MAX703 Datasheet PDF : 10 Pages
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MAX703/MAX704
Low-Cost Microprocessor Supervisory
Circuits with Battery Backup
Pin Description
PIN NAME
FUNCTION
1
VOUT
Supply Output for CMOS RAM. When VCC is above the reset threshold, VOUT connects to VCC through a p-channel
MOSFET switch. When VCC is below the reset threshold, the higher of VCC or VBATT is connected to VOUT.
2 VCC +5V Supply Input
3 GND Ground
4
PFI
Power-Fail Comparator Input. When PFI is less than 1.25V, PFO goes low; otherwise PFO remains high. Connect PFI
to GND or VCC when not used.
5 PFO Power-Fail Comparator Output. It goes low and sinks current when PFI is less than 1.25V; otherwise PFO remains high.
6
MR
Manual Reset Input. Generates a reset pulse when pulled below 0.8V. This active-low input is TTL/CMOS compatible
and can be shorted to ground with a switch. It has an internal 250µA pullup current. Leave floating when not used.
7
RESET
Reset Output. Remains low while VCC is below the reset threshold (4.65V for the MAX703, 4.40V for the MAX704). It
remains low for 200ms after VCC rises above the reset threshold (Figure 2) or MR goes from low to high.
Backup-Battery Input. When VCC falls below the reset threshold, VBATT is switched to VOUT if VBATT is 20mV greater
8 VBATT than VCC. When VCC rises 20mV above VBATT, VCC is switched to VOUT. The 40mV hysteresis prevents repeated
switching if VCC falls slowly.
VBATT
VCC
BATTERY-SWITCHOVER
CIRCUITRY
VOUT
RESET
GENERATOR
RESET
1.25V
MR
PFI
PFO
MAX703
1.25V
MAX704
GND
Figure 1. Block Diagram
+5V
VCC
VRST
0V
VBATT = 3.0V
+5V
VOUT
3.0V
0V
tRST
+5V
RESET
0V
+5V
PFO*
0V
*PFO DEPENDS ON PFI EXCEPT IN BATTERY-BACKUP MODE, WHERE PFO IS LOW.
Figure 2. Timing Diagram
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