HM-6617 Ver la hoja de datos (PDF) - Intersil

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HM-6617

2K x 8 CMOS PROM

Intersil 

HM-6617

Background Information Programming

Algorithm

The HM-6617 CMOS PROM is manufactured with all bits

containing a logical zero (output low). Any bit can be pro-

grammed selectively to a logical one (output high) state by

following the procedure shown below. To accomplish this, a

programmer can be built that meets the specifications

shown, or any of the approved commercial programmers can

be used.

Programming Sequence Of Events

1. Apply a voltage of VCC1 to VCC of the PROM.

2. Read all fuse locations to verify that the PROM is blank

(output low).

3. Place the PROM in the initial state for programming: E =

VIH, P = VIH, G = VIL.

4. Apply the correct binary address for the word to be pro-

grammed. No inputs should be left open circuit.

5. After a delay of tD, apply voltage of VIL to E (pin 18) to ac-

cess the addressed word.

6. The address may be held through the cycle, but must be

held valid at least for a time equal to tD after the falling

edge of E. None of the inputs should be allowed to float

to an invalid logic level.

7. After a delay of tD, disable the outputs by applying a volt-

age of VIH to G (pin 20).

8. After a delay of tD, apply voltage of VIL to P (pin 21).

9. After delay of tD, raise VCC (pin 24) to VCCPROG with a

rise time of tR. All outputs at VIH should track VCC with

VCC -2.0V to VCC +0.3V. This could be accomplished by

pulling outputs at VIH to VCC through pull-up resistors of

value Rn.

Post-Programming Verification

17. Place the PROM in the post-programming verification

mode: E = VIH, G = VIL, P = VIH, VCC (pin 24) = VCC1.

18. Apply the correct binary address of the word to be veri-

fied to the PROM.

19. After a delay of tD, apply a voltage of VIL to E (pin 18).

20. After a delay of tD, examine the outputs for correct data.

If any location fails to verify correctly, the PROM should

be considered a programming reject.

21. Repeat steps 17 through 20 for all possible programming

locations

Post-Programming Read

22. Apply a voltage of VCC2 = 4.0V to VCC (pin 24).

23. After a delay of tD, apply a voltage of VIH to E (pin 18).

24. Apply the correct binary address of the word to be read.

25. After a delay of TAVEL, apply a voltage of VIL to E (pin

18).

26. After a delay of TELQV, examine the outputs for correct

data. If any location fails to verify correctly, the PROM

should be considered a programming reject.

27. Repeat steps 23 through 26 for all address locations.

28. Apply a voltage of VCC2 = 6.0V to VCC (pin 24).

29. Repeat steps 23 through 26 for all address locations.

10. After a delay of tD, pull the output which corresponds to

the bit to be programmed to VIL. Only one bit should be

programmed at a time.

11. After a delay of tPW, allow the output to be pulled to VIH

through pull-up resistor Rn.

12. After a delay of tD, reduce VCC (pin 24) to VCC1 with a fall

time of tF. All outputs at VIH should track VCC with VCC 2.0V

to VCC +0.3V. This could be accomplished by pulling out-

puts at VIH to VCC through pull-up resistors of value Rn.

13. Apply a voltage of VIH to P (pin 21).

14. After a delay of tD, apply a voltage of VIL to G (pin 20).

15. After a delay of tD, examine the outputs for correct data. If

any location verifies incorrectly, repeat steps 4 through 14

(attempting to program only those bits in the word which

verified incorrectly) up to a maximum of eight attempts for

a given word. If a word does not program within eight at-

tempts, it should be considered a programming reject.

16. Repeat steps 3 through 15 for all other bits to be pro-

grammed in the PROM.

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