8102403VA Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Fabricante
8102403VA Datasheet PDF : 8 Pages
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HM-6504
Timing Waveforms
(8)
(7) TELAX
TAVEL
A
ADD VALID
(6)
TEHEL
E
HIGH Z
Q
(1) TELQV
(3)
TELQX
TELEL (18)
TELEH
(5)
(4) TEHQZ
VALID DATA OUTPUT
HIGH
W
TIME
REFERENCE
-1
0
1
2
FIGURE 11. READ CYCLE
(7)
TAVEL
NEXT ADD
TEHEL
(6)
HIGH Z
34
5
TIME REFERENCE
E
-1
H
0
1
L
2
L
3
4
H
5
INPUTS
W
X
H
H
H
H
X
H
TRUTH TABLE
OUTPUT
A
Q
FUNCTION
X
Z
Memory Disabled
V
Z
Cycle Begins, Addresses are Latched
X
X
Output Enabled
X
V
Output Valid
X
V
Read Accomplished
X
Z
Prepare for Next Cycle (Same as -1)
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set-up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled but the data is not valid until during time (T = 2). W
must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the output buffer and all input and ready the RAM for the
next memory cycle (T = 4).
6-130
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