24501BVA Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Fabricante
24501BVA Datasheet PDF : 8 Pages
| |||
HM-6504
AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6504S-9, HM-6504B-9, HM-6504-9)
TA = -55oC to +125oC (HM-6504B-8, HM-6504-8)
SYMBOL
PARAMETER
HM-6504S
MIN MAX
HM-6504B
MIN MAX
HM-6504
MIN MAX
TEST
UNITS CONDITIONS
(1) TELQV Chip Enable Access Time
-
120
-
200
-
300
ns
(Notes 1, 3)
(2) TAVQV Address Access Time
-
120
-
220
-
320
ns
(Notes 1, 3, 4)
(3) TELQX Chip Enable Output Enable
5
-
5
-
5
-
ns
(Notes 2, 3)
Time
(4) TEHQZ Chip Enable Output Disable
-
50
-
80
-
100
ns (Notes 2, 3)
Time
(5) TELEH Chip Enable Pulse Negative 120
-
200
-
300
-
Width
ns
(Notes 1, 3)
(6) TEHEL Chip Enable Pulse Positive
50
-
90
-
120
-
Width
ns
(Notes 1, 3)
(7) TAVEL Address Setup Time
0
-
20
-
20
-
ns
(Notes 1, 3)
(8) TELAX Address Hold Time
40
-
50
-
50
-
ns
(Notes 1, 3)
(9) TWLWH Write Enable Pulse Width
20
-
60
-
80
-
ns
(Notes 1, 3)
(10) TWLEH Write Enable Pulse Setup
70
Time
-
150
-
200
-
ns
(Notes 1, 3)
(11) TWLEL Early Write Pulse Setup
Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(12) TWHEL Write Enable Read Mode
0
-
0
-
0
-
ns
(Notes 1, 3)
Setup Time
(13) TELWH Early Write Pulse Hold Time 40
-
60
-
80
-
ns
(Notes 1, 3)
(14) TDVWL Data Setup Time
0
-
0
-
0
-
ns
(Notes 1, 3)
(15) TDVEL Early Write Data Setup Time 0
-
0
-
0
-
ns (Notes 1, 3)
(16) TWLDX Data Hold Time
25
-
60
-
80
-
ns
(Notes 1, 3)
(17) TELDX Early Write Data Hold Time
25
-
60
-
80
-
ns
(Notes 1, 3)
(18) TELEL Read or Write Cycle Time
170
-
290
-
420
-
ns
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
6-129
Share Link: 