HI5762 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

HI5762

Dual 10-Bit, 60MSPS A/D Converter with Internal Voltage Reference

Intersil 

HI5762

Typical Performance Curves (Continued)

140

ICC

120

100

fS = 60MSPS

1MHz < fIN < 15MHz

80

AICC

60

40 DICC1

20

0

-40

DICC3

-20

DICC2

0

20

40

60

80

TEMPERATURE (°C)

FIGURE 13. SUPPLY CURRENT vs TEMPERATURE

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0

fS = 60MSPS

fIN = 10MHz

TA = +25°C

100 200 300 400 500 600 700 800 900

FREQUENCY (BIN)

FIGURE 14. 2048 POINT FFT PLOT

1023

TABLE 1. A/D CODE TABLE

CODE CENTER

DESCRIPTION

+Full Scale (+FS) -1/4LSB

+FS - 11/4LSB

+3/4 LSB

-1/4 LSB

-FS + 13/4LSB

-Full Scale (-FS) + 3/4LSB

DIFFERENTIAL INPUT

VOLTAGE

(I/QIN+ - I/QIN-)

0.499756V

0.498779V

732.422μV

-244.141μV

-0.498291V

-0.499268V

OFFSET BINARY OUTPUT CODE

MSB

LSB

I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

NOTE:

10. The voltages listed above represent the ideal center of each output code shown with VREFIN = +2.5V.

Detailed Description

Theory of Operation

The HI5762 is a dual 10-bit fully differential sampling pipeline

A/D converter with digital error correction logic. Figure 15

depicts the circuit for the front-end differential-in-differential-

out sample-and-hold (S/H) amplifiers. The switches are

controlled by an internal sampling clock which is a

non-overlapping two phase signal, Φ1 and Φ2, derived from

the master sampling clock. During the sampling phase, Φ1,

the input signal is applied to the sampling capacitors, CS. At

the same time the holding capacitors, CH, are discharged to

analog ground. At the falling edge of Φ1 the input signal is

sampled on the bottom plates of the sampling capacitors. In

the next clock phase, Φ2, the two bottom plates of the

sampling capacitors are connected together and the holding

capacitors are switched to the op amp output nodes. The

charge then redistributes between CS and CH completing one

sample-and-hold cycle. The front end sample-and-hold output

is a fully-differential, sampled-data representation of the

analog input. The circuit not only performs the sample-and-

hold function but will also convert a single-ended input to a

fully-differential output for the converter core. During the

sampling phase, the I/QIN pins see only the on-resistance of a

switch and CS. The relatively small values of these

components result in a typical full power input bandwidth of

250MHz for the converter.

I/QIN+

I/QIN-

Φ1

Φ2

Φ1

Φ1

CS

CS

Φ1

CH

-+

+-

CH

Φ1

VOUT+

VOUT-

Φ1

FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD

11

FN4318.3

January 22, 2010

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