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HI5804EVAL

12-Bit, 5 MSPS A/D Converter

Intersil 

HI5804

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio of the fundamental RMS amplitude to the

RMS amplitude of the next largest spur or spectral

component in the spectrum below fS/2.

Transient Response

Transient response is measured by providing a full scale

transition to the analog input of the ADC and measuring the

number of cycles it takes for the output code to settle within

12-bit accuracy.

Overvoltage Recovery

Overvoltage Recovery is measured by providing a full scale

transition to the analog input of the ADC which overdrives

the input by 200mV, and measuring the number of cycles it

takes for the output code to settle within 12-bit accuracy.

Full Power Input Bandwidth (FPBW)

Full power input bandwidth is the frequency at which the

amplitude of the digitally reconstructed output has

decreased 3dB below the amplitude of the input sine wave.

The input sine wave has a peak-to-peak amplitude equal to

the difference between the two internal voltage references.

The bandwidth given is measured at the specified sampling

frequency.

Timing Definitions

Refer to Figure 1 and Figure 2 for these definitions.

Aperture Delay (tAP)

Aperture delay is the time delay between the external sam-

ple command (the falling edge of the clock) and the time at

which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

Aperture Jitter (tAJ)

Aperture Jitter is the RMS variation in the aperture delay due

to variation of internal clock path delays.

Data Hold Time (tH)

Data hold time is the time to where the previous data (N - 1)

is no longer valid.

Data Output Delay Time (tOD)

Data output delay time is the time to where the new data (N)

is valid.

Data Latency (tLAT)

After the analog sample is taken, the digital data is output on

the bus after the third cycle of the clock. This is due to the

pipeline nature of the converter where the data has to ripple

through the stages. This delay is specified as the data latency.

After the data latency time, the data representing each

succeeding sample is output at the following clock pulse. The

digital data lags the analog input sample by 3 clock cycles.

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