HI7191 Ver la hoja de datos (PDF) - Renesas Electronics

Número de pieza

componentes Descripción

Fabricante

HI7191

24-Bit, High Precision, Sigma Delta A/D Converter

Renesas Electronics 

HI7191

Electrical Specifications

PARAMETER

AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND = 0V, VCM = AGND,

PGIA Gain = 1, OSCIN = 10MHz, Bipolar Input Range Selected, fN = 10Hz (Continued)

TEST CONDITIONS

MIN

TYP

MAX

Input Logic Current, II

Input Capacitance, CIN

DIGITAL OUTPUTS

VIN = 0V, +5V

VIN = 0V

-

1.0

10

-

5.0

-

Output Logic High Voltage, VOH

Output Logic Low Voltage, VOL

Output Three-State Leakage Current,

IOZ

Digital Output Capacitance, COUT

TIMING CHARACTERISTICS

IOUT = -100A (Note 7)

IOUT = 3mA (Note 7)

VOUT = 0V, +5V (Note 7)

2.4

-

-

-

-

0.4

-10

1

10

-

10

-

SCLK Minimum Cycle Time, tSCLK

SCLK Minimum Pulse Width, tSCLKPW

CS to SCLK Precharge Time, tPRE

DRDY Minimum High Pulse Width

(Notes 2, 7)

200

-

-

50

-

-

50

-

-

500

-

-

Data Setup to SCLK Rising Edge

(Write), tDSU

Data Hold from SCLK Rising Edge

(Write), tDHLD

Data Read Access from Instruction Byte

Write, tACC

Read Bit Valid from SCLK Falling Edge,

tDV

Last Data Transfer to Data Ready

Inactive, tDRDY

RESET Low Pulse Width

(Note 7)

(Note 7)

(Note 7)

(Note 2)

50

-

-

0

-

-

-

-

40

-

-

40

-

35

-

100

-

-

SYNC Low Pulse Width

(Note 2)

100

-

-

Oscillator Clock Frequency

(Note 2)

0.1

-

10

Output Rise/Fall Time

(Note 2)

-

-

30

Input Rise/Fall Time

(Note 2)

-

-

1

POWER SUPPLY CHARACTERISTICS

IAVDD

IAVSS

IDVDD

Power Dissipation, Active PDA

Power Dissipation, Standby PDS

PSRR

SCLK = 4MHz

SB = ‘0’

SB = ‘1’

(Note 3)

-

-

1.5

-

-

2.0

-

-

3.0

-

15

32.5

-

5

-

-

70

-

NOTES:

2. Parameter guaranteed by design or characterization, not production tested.

3. Applies to both bipolar and unipolar input ranges.

4. These errors can be removed by re-calibrating at the desired operating temperature.

5. Applies after system calibration.

6. Fully differential input signal source is used.

7. See Load Test Circuit, Figure 10, R1 = 10k, CL = 50pF.

8. 1 LSB = 298nV at 24 bits for a Full Scale Range of 5V.

9. VREF = VRHI - VRLO.

10. These errors are on the order of the output noise shown in Table 1.

11. All inputs except OSC1. The OSC1 input VIH is 3.5V minimum.

UNITS

A

pF

V

V

A

pF

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

MHz

ns

s

mA

mA

mA

mW

mW

dB

FN4138 Rev 8.00

June 1, 2006

Page 5 of 25

Share Link: