HIP1012ACB Ver la hoja de datos (PDF) - Renesas Electronics

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HIP1012ACB

Dual Power Distribution Controller

Renesas Electronics 

HIP1012A

TABLE 1.

RILIM RESISTOR

15k

NOMINAL OC VTH

150mV

10k

100mV

7.5k

75mV

4.99k

50mV

NOTE: Nominal OC Vth = Rilim x 10A.

TABLE 2.

CTIM CAPACITOR

NOMINAL TIME OUT PERIOD

0.022F

4.4ms

0.047F

9.4ms

0.1F

20ms

NOTE: Nominal time-out period in seconds = CTIM x 200k

The HIP1012A responds to a load short (defined as a current

level 3X the OC set point) immediately, driving the relevant

N-Channel MOSFET gate to 0V in less than 10s. The gate

voltage is then slowly ramped up turning on the N-Channel

MOSFET to the programmed current limit level; this is the start

of the time out period. The programmed current level is held until

either the OC event passes or the time out period expires. If the

former is the case then the N-Channel MOSFET is fully

enhanced and the CTIM charging current is diverted away from

the capacitor. If the time out period expires prior to OC resolution

then both gates are quickly pulled to 0V turning off both N-

Channel MOSFETs simultaneously.

Upon any UV condition the PGOOD signal will pull low when

tied high through a resistor to the logic supply. This pin is a fault

indicator but not the OC latch off indicator. For an OC latch off

indication, monitor CTIM, pin 10. This pin will rise rapidly to 12V

once the time out period expires. See Simplified Block Diagram

on page 2 for OC latch off circuit suggestion.

The HIP1012A is reset by a rising edge on either PWRON pin

and is turned on by either PWRON pin being driven low. The

HIP1012A can control either +12V/5V or +3.3V/+5V supplies.

Tying the PWRON1 pin to VDD, invokes the +3.3V/+5V voltage

mode. In this mode, the external charge pump capacitor is not

needed and Cpump, pin 11 is tied directly to VDD.

HIP1012A Application Considerations

Current Regulation vs current trip often causes confusion

when using this and other ICs with a Current Regulation (CR)

feature. The CR level is the level at which the HIP1012 will hold

an overcurrent load for the programmed duration. This level is

programmable by the RLIM and RSENSE resistors values. As

the current being monitored by the HIP1012A approaches a

level >85% of the CR level the HIP1012A may trip-off due to

variances in manufacturing and the design of the low gain high

speed input comparators. In addition with the high levels of

inrush current e.g., highly capacitive loads and motor startup

currents, choosing the current limiting level is crucial to provide

FN4419 Rev 6.00

March 2004

both protection and still allow for this inrush current without

latching off. Consider this in addition to the time out delay when

choosing MOSFETs for your design. To these ends it is

suggested that CR levels be programmed to 150% of nominal

load.

When using the HIP1012A in the 12V and 5V mode additional

VDD decoupling may be necessary to prevent a power on reset

due to a sag on VDD pin upon an OC latch off. The addition of a

capacitor from VDD to GND may often be adequate but a small

value isolation resistor may also be necessary (see the

Simplified Block Diagram on page 2).

Current loop stabilization is facilitated through a small value

resistor in series with the gate timing capacitor. As the

HIP1012A drives a highly inductive current load, instability

characterized by the gate voltage repeatedly ramping up and

down may appear. A simple method to enhance stability is

provided by the substitution of a larger value gate resistor.

Typically this situation can be avoided by eliminating long point

to point wiring to the load.

Random resets occur if the HIP1012A sense pins are pulled

below ground when turning off a highly inductive load. Place a

large load capacitor (10-50F) on the output or ISEN clamping

diodes to ground to eliminate.

During the Time Out delay period with the HIP1012A in current

limit mode, the VGS of the external N-Channel MOSFETs is

reduced driving the N-Channel MOSFET switch into a high

rDS(ON) state. Thus avoid extended time out periods as the

external N-Channel MOSFETs may be damaged or destroyed

due to excessive internal power dissipation. Refer to the

MOSFET manufacturer’s data sheet for SOA information.

External Pull Down resistors from the xISEN pins to ground

will prevent the voltage outputs from floating up due to leakage

current through the external switch FET body diode when the

FETs are disabled and the outputs are open.

Physical layout of Rsense resistors is critical to avoid the

possibility of false overcurrent occurrences. Ideally trace routing

between the Rsense resistors and the HIP1012A is direct and

as short as possible with zero current in the sense lines as

shown below.

CORRECT

INCORRECT

TO ISEN AND

RISET

CURRENT

SENSE RESISTOR

FIGURE 1. SENSE RESISTOR PCB LAYOUT

Page 6 of 15

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