HFA1405 Ver la hoja de datos (PDF) - Renesas Electronics
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HFA1405 Datasheet PDF : 15 Pages
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HFA1405
package type. Graphs not labeled with a specific package
type are applicable to all packages.
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and RF .
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF , in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF. The HFA1405 design is
optimized for RF = 402/510 (PDIP/SOIC) at a gain of +2.
Decreasing RF decreases stability, resulting in excessive
peaking and overshoot (Note: Capacitive feedback causes
the same problems due to the feedback impedance
decrease at higher frequencies). However, at higher gains
the amplifier is more stable so RF can be decreased in a
trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth. For good channel-to-
channel gain matching, it is recommended that all resistors
(termination as well as gain setting) be 1% tolerance or
better.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN
(ACL)
RF ()
PDIP/SOIC
BANDWIDTH (MHz)
PDIP/SOIC
-1
310/360
360/420
+1
510 (+RS = 510)/
464 (+RS = 649)
+2
402/510
300/375
400/560
+5
NA/200
NA/330
+6
500/500 (Note)
100/140
+10
NA/180
NA/140
NOTE: RF = 500 is not the optimum value. It was chosen to
match the RF of the CLC414 and CLC415, for performance
comparison purposes. Performance at AV = +6 may be increased by
reducing RF below 500.
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be 50This is especially
important in inverting gain configurations where the non-
inverting input would normally be connected directly to GND.
Pulse Undershoot
The HFA1405 utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device
replaces the traditional PNP pulldown transistor. The
composite device switches modes after crossing 0V,
FN3604 Rev 9.00
March 1, 2005
resulting in added distortion for signals swinging below
ground, and an increased undershoot on the negative
portion of the output waveform (see Figure 6 and Figure 9).
This undershoot isn’t present for small bipolar signals, or
large positive signals (see Figure 4 and Figure 5).
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10F) tantalum in parallel with a small value
(0.1F) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance, parasitic or
planned, connected to the output must be minimized, or
isolated as discussed in the next section.
Care must also be taken to minimize the capacitance to
ground at the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and eventual instability. To reduce this
capacitance the designer should remove the ground plane
under traces connected to -IN, and keep connections to -IN
as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus limiting
system bandwidth well below the amplifier bandwidth of
560MHz. By decreasing RS as CL increases (as illustrated in
the curve), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth still decreases
as the load capacitance increases.
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