HB5425161BTT-75B Ver la hoja de datos (PDF) - Elpida Memory, Inc

Número de pieza

componentes Descripción

Fabricante

HB5425161BTT-75B

256M SSTL_2 interface DDR SDRAM

Elpida Memory, Inc 

HM5425161B, HM5425801B, HM5425401B Series

Pin Functions (2)

DM, DMU/DML (input pins): DM (the HM5425801B and the HM5425401B), DMU/DML (the

HM5425161B) are the reference signals of the data input mask function. DMs are sampled at the cross point

of DQS and VREF. DMU/DML provide the byte mask function. When DMU/DML = High, the data input at

the same timing are masked while the internal burst counter will be count up. DML controls the lower byte

(DQ0 to DQ7) and DMU controls the upper byte (DQ8 to DQ15) of write data.

DQ0 to DQ15 (input and output pins): Data are input to and output from these pins (the DQ0 to the DQ15;

the HM5425161B, the DQ0 to the DQ7; the HM5425801B, the DQ0 to the DQ3; the HM5425401B).

DQS, DQSU/DQSL (input and output pin): DQS (the HM5425801B and the HM5425401B),

DQSU/DQSL (the HM5425161B) provide the read data strobes (as output) and the write data strobes (as

input). DQSL is the lower byte (DQ0 to DQ7) data strobe signal, DQSU is the upper byte (DQ8 to DQ15)

data strobe signal.

VCC and VCCQ (power supply pins): 2.5 V is applied. (VCC is for the internal circuit and VCCQ is for the

output buffer.)

VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the

output buffer.)

Data Sheet E0086H20

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