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KSZ9031MNX

Gigabit Ethernet Transceiver with GMII/MII Support

Microsemi Corporation 

KSZ9031MNX

TABLE 2-1: SIGNALS - KSZ9031MNX (CONTINUED)

Pin

Number

43

44

45

46

47

48

49

50

51

52

53

54

Pin

Name

RXD1/

MODE1

RXD0/

MODE0

RX_DV/

CLK125_EN

DVDDH

RX_ER

RX_CLK/

PHYAD2

CRS

MDC

MDIO

COL

INT_N/

PME_N2

DVDDL

Type

Note

2-1

Description

GMII mode: GMII RXD1 (Receive Data 1) output

MII mode: MII RXD1 (Receive Data 1) output

I/O Config mode: The voltage on this pin is sampled and latched during the

power-up/reset process to determine the value of MODE1. See the Strapping

Options - KSZ9031MNX section for details.

GMII mode: GMII RXD0 (Receive Data 0) output

MII mode: MII RXD0 (Receive Data 0) output

I/O Config mode: The voltage on this pin is sampled and latched during the

power-up/reset process to determine the value of MODE0. See the Strapping

Options - KSZ9031MNX section for details.

GMII mode: GMII RX_DV (Receive Data Valid) output

MII mode: MII RX_DV (Receive Data Valid) output

I/O Config mode: The voltage on this pin is sampled and latched during the

power-up/reset process to determine the value of CLK125_EN. See the

Strapping Options - KSZ9031MNX section for details.

P

3.3V, 2.5V, or 1.8V digital VDD_IO

O GMII mode: GMII RX_ER (Receive Error) output

MII mode: MII RX_ER (Receive Error) output

GMII mode: GMII RX_CLK (Receive Reference Clock) output

MII mode: MII RX_CLK (Receive Reference Clock) output

I/O Config mode: The voltage on this pin is sampled and latched during the

power up/reset process to determine the value of PHYAD[2]. See the Strap-

ping Options - KSZ9031MNX section for details.

O

Ipu

Ipu/O

O

GMII mode: GMII CRS (Carrier Sense) output

MII mode: MII CRS (Carrier Sense) output

Management data clock input

This pin is the input reference clock for MDIO (Pin 51).

Management data input/output

This pin is synchronous to MDC (Pin 50) and requires an external pull-up

resistor to DVDDH (digital VDD_IO) in a range from 1.0 kΩ to 4.7 kΩ.

GMII mode: GMII COL (Collision Detected) output

MII mode: MII COL (Collision Detected) output

Interrupt output: Programmable interrupt output, with Register 1Bh as the

Interrupt Control/Status Register, for programming the interrupt conditions

and reading the interrupt status. Register 1Fh, Bit [14] sets the interrupt out-

put to active low (default) or active high.

O

PME_N output: Programmable PME_N output (pin option 2). When asserted

low, this pin signals that a WOL event has occurred.

For Interrupt (when active low) and PME functions, this pin requires an exter-

nal pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0 kΩ to

4.7 kΩ.

This pin is not an open-drain for all operating modes.

P

1.2V digital VDD

DS00002096C-page 10

 2016 Microchip Technology Inc.

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