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CYM1861 Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción
Fabricante
CYM1861
Cypress
Cypress Semiconductor Cypress
CYM1861 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
PRELIMINARY
CYM1861
2,048K x 32 Static RAM Module
Features
• High-density 64-megabit SRAM module
• 32-bit Standard Footprint supports densities from 16K
x 32 through 2M x 32
• High-speed SRAMs
— Access time of 35 ns
72 pins
• Available in SIMM format
Functional Description
The CYM1861 is a high-performance 64-megabit static RAM
module organized as 2,048K words by 32 bits. This module is
constructed from sixteen 1,024K x 4 SRAMs in SOJ packages
mounted on an epoxy laminate substrate. Four chip selects are
Logic Block Diagram
A0– A19
OE
WE
Buffer 20
CS1 –CS4
PAL
A20
1M x 4
SRAM
4 I/O4 –I/O7
4 I/O0 –I/O3
1M x 4
SRAM
4 I/O12– I/O15
4 I/O8 –I/O11
1M x 4
SRAM
4 I/O20 – I/O23
4 I/O16–I/O19
1M x 4
SRAM
4 I/O28 –I/O31
4 I/O24– I/O27
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Shaded area contains advance information.
used to independently enable the four bytes. Reading or writ-
ing can be executed on individual bytes or any combination of
multiple bytes through proper use of selects.
The CYM1861 is designed for use with standard 72-pin SIMM
sockets. The pinout is downward compatible with the 64-pin
JEDEC SIMM module family (CYM1821, CYM1831,
CYM1836, and CYM1841). Thus, a single motherboard de-
sign can be used to accommodate memory depth ranging from
16K words (CYM1821) to 2,048K words (CYM1861). The
CYM1861 is offered in vertical SIMM configuration and is avail-
able with tin-lead edge contacts.
Presence detect pins (PD0–PD3) are used to identify module
memory density in applications where modules with alternate
word depths can be interchanged.
Pin Configuration
ZIP/SIMM
Top View
PD0 - OPEN
PD1 - GND
PD2 - GND
PD3 - OPEN
1M x 4
SRAM
4 I/O4–I/O7
I/O0–I/O3
4
1M x 4
SRAM
4 I/O12– I/O15
4 I/O8 –I/O11
1M x 4
SRAM
4 I/O20 – I/O23
4 I/O16–I/O19
1M x 4
SRAM
4 I/O28 –I/O31
4 I/O24– I/O27
1861–1
NC
PD3
PD0
I/O0
I/O1
I/O2
I/O3
VCC
AA78
A9
I/O4
I/O5
I/O6
I/O7
WE
A14
CS1
CS3
A16
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
A19
NC
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15
16 17
18 19
20 21
22 23
24 25
26 27
28 29
30 31
32 33
34 35
36
37
38 39
40 41
42 43
44 45
46 47
48 49
50 51
52 53
54 55
56 57
58 59
60 61
62 63
64 65
66 67
68 69
70 71
72
NC
PD2
GND
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
CS2
CS4
A17
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
A18
A20
1861–2
1861-25
25
1200
480
1861-35
35
960
480
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 4, 1998

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