ADADC85S12 Ver la hoja de datos (PDF) - Analog Devices
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ADADC85S12 Datasheet PDF : 12 Pages
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AD ADC84/AD ADC85
NOTES
1. THE CONVERT START PULSE WIDTH IS 100ns MIN AND MUST REMAIN LOW DURING A CONVERSION. THE CONVERSION
IS INITIATED BY THE “TRAILING EDGE” OF THE CONVERT COMMAND.
2. 10μs FOR 12 BITS (AD ADC84/AD ADC85).
3. MSB DECISION.
4. LSB DECISION 20ns PRIOR TO THE STATUS GOING LOW.
*BIT DECISIONS.
Figure 10. Timing Diagram (Binary Code 011001110110)
DIGITAL OUTPUT DATA
Parallel data from TTL storage registers are in negative true
form. Parallel data coding is complementary binary for unipolar
ranges and either complementary offset binary or
complementary twos complement binary, depending on
whether BIT 1 (Pin 12) or its logical inverse BIT 1 (Pin 13) is
used as the MSB. Parallel data becomes valid approximately
40 ns before the STATUS flag returns to Logic “0”, permitting
parallel data transfer to be clocked on the “1” to “0” transition of
the STATUS flag.
Parallel data outputs change state on positive-going clock edges.
There are 13 negative-going clock edges in the complete 12-bit
conversion cycle, as shown in Figure 10. The first edge shifts an
invalid bit into the register, which is shifted out on the 13th
negative-going clock edge.
Short Cycle Input
A short cycle input, Pin 14, permits the timing cycle shown in
Figure 10 to be terminated after any number of desired bits has
been converted, permitting somewhat shorter conversion times
in applications not requiring full 12-bit resolution. When 12-bit
resolution is required, Pin 14 is connected to +5 V (Pin 16).
When 10-bit resolution is required, Pin 14 is connected to Bit 11
output Pin 2. The conversion cycle then terminates, and the
STATUS flag resets after the Bit 10 decision (t10 + 40 ns in
timing diagram of Figure 10). Short cycle pin connections and
associated maximum 12-, 10-, and 8-bit conversion times are
summarized in Table 2.
Rev. B | Page 7 of 12
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