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NJU6631ACH

16-CHARACTER 1-LINE DOT MATRIX LCD CONTROLLER DRIVER

Japan Radio Corporation  

NJU6631A

(ｇ) Function Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 0 0 1 DL A * M1 M0 * = Don’t Care

Function set instruction which sets the interface data length, the addressing Mode for the DD RAM, 1-line or

2-line display, and Pin configuration mode, is executed when the code "1" is written into DB5 and the codes of

(DL), (A), (M1) and (M0) are written into DB4(DL), DB3(A), DB1(M1) and DB0(M0), as shown below (character

font is fixed 5 x 7 dots).

(DL) sets the interface data length, (A) sets the DD RAM address mode (00)H through (0F)H or (00)H through

(07)H and (40)H through (47)H, (M1) sets the number of display line either the 1-line or 2-line display, and (M0)

sets the Pin configuration for Common and Segment drivers as shown in coordinates.

NOTE

This function set instruction must be performed at the head of the program prior to all other

existing instructions (except Busy flag/Address read). This function set instruction can not be

executed afterwards unless the interface data length change.

DL

Function

1

Set the interface data length to 8 bits (DB7 to DB0).

0

Set the interface data length to 4 bits (DB7 to DB4).

The data must be sent or received twice.

A

Function

0

Set the Addressing Mode 1 for the DD RAM.

1

Set the Addressing Mode 2 for the DD RAM.

M1

Function

0

Set the 16-Character 1-Line Display.

1

Set the 8-Character 2-Line Display.

M0

Function

0

Set the Pin configuration mode A for Common and Segment Driver. Refer to

1

Set the Pin configuration mode B for Common and Segment Driver. coordinates

(h) Set CG RAM Address

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 0 1 * A A A A A * = Don’t Care

Higher order bit

Lower order bit

Set CG RAM address instruction is executed when the code "1" is written into DB6 and the address is

written into DB4 to DB0 as shown above.

The address data mentioned by binary code "AAAAA" is written into the address counter (AC) together with

the CG RAM addressing condition. After this instruction execution, the data writing/reading is performed

into/from the CG RAM.

(i) Set DD RAM Address

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Code 0 0 1 A A A A A A A

Higher order bit

Lower order bit

Set DD RAM address instruction is executed when the code "1" is written into DB7 and the address is written

into DB6 to DB0 as shown above.

The address data mentioned by binary code "AAAAAAA" is written into the address counter (AC) together

with the DD RAM addressing condition. After this instruction, the data writing/reading is performed into/from

the DD RAM.

Note : When the "Addressing mode 1" selection, (00)H through (0F)H are available but (10)H through (7F)H are

ignored. When the "Addressing mode 2" selection, (00)H through (07)H and (40)H through (47)H are

available but (08)H through (3F)H and (48)H through (7F)H are ignored.

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