NJU6631ACH Ver la hoja de datos (PDF) - Japan Radio Corporation

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Fabricante

NJU6631ACH

16-CHARACTER 1-LINE DOT MATRIX LCD CONTROLLER DRIVER

Japan Radio Corporation  

NJU6631A

(3) Instruction

The NJU6631A incorporates two registers, an Instruction Register (IR) and a Data Register (DR).

These two registers store control information temporarily to allow interface between NJU6631A and MPU or

peripheral ICs operating different cycles. The operation of NJU6631A is determined by this control signal from

MPU.

The control information includes register selection signals (RS), read/write signals (R/W) and data bus

signals (DB0 to DB7).

Table 4. shows each instruction and its operating time.

Note) The execution time mentioned in Table 4. based on fcp or fosc=270kHz.

If the oscillation frequency is changed, the execution time is also changed.

Table 4. Table of Instructions

Instructions

Maker Test

Clear Display

Return Home

Entry Mode Set

Display On/Off

Control

Cursor or

Display Shift

Function Set

Set CG RAM

address

Set DD RAM

address

Read Busy Flag

& Address

Write Data to

CG or DD RAM

Read Data to

CG or DD RAM

Explanation of

Abbreviation

Code

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description

Exec

Time

0

0

0

0

0

0

0

0

0

0

All “0” code is using for maker

testing.

-

0

0

0

0

0

0

0

0

0

1

Display clear and

address 0 in AC.

sets

DD

RAM

1.52ms

Sets DD RAM address 0 in AC and

returns display being shifted to

0 0 0 0 0 0 0 0 1 * original position.

37us

DD RAM contents remain

unchanged.

Sets cursor move direction and

specifies shift of display are

0 0 0 0 0 0 0 1 I/D S performed in data read/write.

37us

I/D=1:Increment, I/D=0:Decrement

S=1:Accompanies display shift.

Sets of display On/Off(D), cursor

0 0 0 0 0 0 1 D C B On/Off(C) and blink of cursor 37us

position character(B).

Moves cursor and shifts display

without changing DD RAM contents

0

00

0

0

1 S/C R/L *

*

S/C=1 : Display shift

S/C=0 : Cursor shift

56us

R/L=1 : Shift to the right

R/L=0 : Shift to the left

Sets interface data length(DL),

Display address mode(A).

DL=1 : 8 bits, DL=0 : 4 bits

A=0 : Addressing mode 1

0 0 0 0 1 DL A * M1 M0 A=1 : Addressing mode 2

37us

M1=0: 16-Character 1-Line

M1=1: 8-Character 2-Line

M0=0: Pin configuration mode A

M0=1: Pin configuration mode B

0001 *

Sets CG RAM address. After this

ACG

instruction, the data is transferred 37us

on CG RAM.

001

Sets DD RAM address. After this

ADD

instruction, the data is transferred 37us

on DD RAM.

0 1 BF

ACDD

Reads busy flag and AC contents.

BF=1 : Internally operating

**

ACCG

BF=0 : Can accept instruction

1

0

*

Write Data(DD RAM)

Writes data into CG or DD RAMs.

* * Write Data(CG RAM)

0us

37us

1

1

*

Read Data(DD RAM)

Reads data from CG or DD RAMs.

* * Read Data(CG RAM)

56us

DD RAM : Display data RAM, CG RAM : Character generator RAM

ACG : CG RAM address, ADD : DD RAM address, Corresponds to cursor address

AC : Address counter used for both of DD and CG RAMs

* = Don’t Care

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