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HI1175JCP Ver la hoja de datos (PDF) - Intersil

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HI1175JCP Datasheet PDF : 13 Pages
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Functional Block Diagram
HI1175
OE 1
DVSS 2
D0 (LSB) 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 (MSB) 10
DVDD 11
CLK 12
LOWER
DATA
LATCHES
UPPER
DATA
LATCHES
LOWER
ENCODER
(4-BIT)
LOWER
ENCODER
(4-BIT)
UPPER
ENCODER
(4-BIT)
CLOCK GENERATOR
REFERENCE VOLTAGE
LOWER
COMPARATORS
WITH S/H (4-BIT)
LOWER
COMPARATORS
WITH S/H (4-BIT)
UPPER
COMPARATORS
WITH S/H (4-BIT)
24 DVSS
23 VRB
22 VRBS
0.6V (Typ)
21 AVSS
20 AVSS
19 VIN
18 AVDD
17 VRT
16 VRTS
2.6V (Typ)
15 AVDD
14 AVDD
13 DVDD
Typical Application Schematic
HC04
+5V
R11
R12
ICL8069
CA158A
R4
+
- R13
R3
R5
+
-
CLOCK IN
+5V
C9 +
4.7µF
C10
13
12
0.1µF
14
11
15
10
CA158A
16
9
17
8
C12
C8
HA2544
0.1µF
18
7
VIN
+
-
HI1175
19
6
R1
R2
20
5
21
4
CLK
D7 (MSB)
D6
D5
D4
D3
D2
D1
C11
0.1µF
22
23
C7 +
24
4.7µF
3
D0 (LSB)
2
1
: Ceramic Chip Capacitor 0.1µF
+5V
: Analog GND
: Digital GND
NOTE: It is necessary that AVDD and DVDD pins be driven from the same supply. The gain of analog input signal can be changed by adjusting
the ratio of R2 to R1.
4-1070

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