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PI74LCX16652(1997) Ver la hoja de datos (PDF) - Pericom Semiconductor

Número de pieza
componentes Descripción
Fabricante
PI74LCX16652
(Rev.:1997)
Pericom-Semiconductor
Pericom Semiconductor Pericom-Semiconductor
PI74LCX16652 Datasheet PDF : 6 Pages
1 2 3 4 5 6
PI74LCX16652
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Fast CMOS 16-Bit
Registered Transceivers
Product Features
• Functionally compatible with FCT3, LVT, and 74 series
16652 families of products
• Tri-State outputs
• 5V Tolerant inputs and outputs
• 2.0V-3.6V VCC supply operation
• Balanced sink and source output drives (24 mA)
• Low ground bounce outputs
• Supports live insertion
• ESD Protection exceeds 2000V, Human Body Model
200V, Machine Model
• Packages available:
– 56-pin 240-mil wide plastic TSSOP (A)
– 56-pin 300-mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor's PI74LCX series of logic circuits are
produced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74LCX16652 is 16-bit non-inverting, bidirectional bus
transceiver organized as two independent 8-bit bus transceivers
designed with 3-state D-type flip-flops and control circuitry arranged
for multiplexed transmission of data directly from the data bus or
from the internal storage registers. Each 8-bit transceiver utilizes the
enable controls (xOEAB and x OEBA) to control the transceiver
functions. The Select (xSAB and xSBA) control pins are used to
select either real-time or stored data transfer. The circuitry used for
select control will eliminate the typical decoding glitch that occurs
in a multiplexer during the transition between real-time and stored
data. A low input level selects real-time data and a high selects
stored data.
The PI74LCX16652 can be driven from either 3.3V or 5.0V devices
allowing this device to be used as a translator in a mixed
3.3/5.0V system.
Logic Block Diagram
1OEAB
1OEBA
1CLKBA
1SBA
1CLKAB
1SAB
1A0
A REG
D
C
B REG
D
C
2OEAB
2OEBA
2CLKBA
2SBA
2CLKAB
2SAB
2A0
1B0
A REG
D
C
B REG
D
C
2B0
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
1
PS2094A 02/19/97

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