MB90350 Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

MB90350

F2MC-16LX 16-bit Microcontroller

Cypress Semiconductor 

MB90350 Series

1. Product Lineup 1

Part Number

Parameter

CPU

MB90F351,

MB90F352

MB90F351S,

MB90F352S

MB90F351A, MB90F351TA, MB90F351AS, MB90F351TAS,

MB90F352A MB90F352TA MB90F352AS MB90F352TAS

F2MC-16LX CPU

System clock

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)

ROM

Flash memory

64Kbytes :MB90F351(S)

128Kbytes :MB90F352(S)

Dual operation flash memory

64Kbytes :MB90F351A(S), MB90F351TA(S)

128Kbytes :MB90F352A(S), MB90F352TA(S)

RAM

4 Kbytes

Emulator-specific power

supply*

—

Sub clock pin

(X0A, X1A)

Yes

No

Yes

No

(Max 100 kHz)

Clock monitor

function

No

Low voltage/CPU

operation detection

No

reset

No

Yes

No

Yes

Operating

voltage range

3.5 V to 5.5 V : at normal operating (not using A/D converter)

4.0 V to 5.5 V : at using A/D converter/Flash programming

4.5 V to 5.5 V : at using external bus

Operating

temperature range

40 °C to 105 °C (125 °C up to

16 MHz machine clock)

40 °C to 125 °C

Package

LQFP-64

2 channels

UART

I2C (400 Kbps)

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

1 channel

A/D Converter

16-bit Reload Timer

(4 channels)

15 channels

10-bit or 8-bit resolution

Conversion time : Min 3 s includes sample time (per one channel)

Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys  Machine clock frequency)

Supports External Event Count function.

16-bit I/O Timer

(2 channels)

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.

I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.

Signals an interrupt when overflowing.

Supports Timer Clear when a match with Output Compare (Channel 0, 4) .

Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27

(fsys  Machine clock frequency)

16-bit Output

Compare

4 channels

Signals an interrupt when 16-bit I/O Timer matches with output compare registers.

A pair of compare registers can be used to generate an output signal.

16-bit Input Capture

6 channels

Retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.

(Continued)

Document Number: 002-07872 Rev. *A

Page 4 of 83

Share Link: