MC100LVEL38DWR2 Ver la hoja de datos (PDF) - ON Semiconductor

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MC100LVEL38DWR2

3.3VECL ÷2, ÷4/6 Clock Generation Chip

ON Semiconductor 

CLK

Q (÷2)

Q (÷4)

Q (÷6)

Phase_Out (÷4)

Phase_Out (÷6)

MC100LVEL38

Figure 3. Timing Diagrams

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

VCC

PECL Mode Power Supply

VEE

NECL Mode Power Supply

VI

PECL Mode Input Voltage

NECL Mode Input Voltage

Iout

Output Current

VEE = 0 V

VCC = 0 V

VEE = 0 V

VCC = 0 V

Continuous

Surge

VI  VCC

VI  VEE

8 to 0

V

−8 to 0

V

6 to 0

V

−6 to 0

V

50

mA

100

mA

IBB

VBB Sink/Source

TA

Operating Temperature Range

Tstg

Storage Temperature Range

qJA

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SOIC−20

SOIC−20

± 0.5

−40 to +85

−65 to +150

90

60

mA

°C

°C

°C/W

°C/W

qJC

Thermal Resistance (Junction−to−Case)

Standard Board

SOIC−20

Tsol

Wave Solder

Pb <2 to 3 sec @ 248°C

Pb−Free <2 to 3 sec @ 260°C

30 to 35

265

265

°C/W

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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