CXL5504M Ver la hoja de datos (PDF) - Sony Semiconductor

Número de pieza

componentes Descripción

Fabricante

CXL5504M

CMOS-CCD 1H Delay Line for NTSC

Sony Semiconductor 

CXL5504M/P

(2) This is the IC supply current value during clock and signal input.

(3) GLPN, GLNP are output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.

(Example of calculation)

OUT pin output voltage (PN mode) [mVp-p]

GLPN = 20 log

[dB]

500 [mVp-p]

(4) Indicates the dissipation at 3.57MHz in relation to 200kHz.

From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the

output voltage at OUT pin when a 150mVp-p, 3.57MHz sine wave is fed to same, calculation is made

according to the following formula. The input part bias is tested at 2.1V.

(Example of calculation)

OUT pin otuput voltage (PN mode, 3.57MHz) [mVp-p]

fPN = 20 log

[dB]

OUT pin output voltage (PN mode, 200kHz) [mVp-p]

(5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure below is

input are tested at the vector scope.

143mV

357mV

500mV

143mV

1H 63.56µs

Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)

(6) The internal clock component to the output signal during no-signal input and the leakage of that high

harmonic component are tested. The input part bias is tested at VINPN + 0.5V and VINNP for PN and NP

modes respectively.

Test value

(mVp-p)

–4–

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