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M4A5-384/128-5SAC Ver la hoja de datos (PDF) - Lattice Semiconductor

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M4A5-384/128-5SAC Datasheet PDF : 63 Pages
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ispMACHâ„¢ 4A CPLD Family
High Performance E2CMOS®
In-System Programmable Logic
FEATURES
â—† High-performance, E2CMOS 3.3-V & 5-V CPLD families
â—† Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and reï¬t feature
— SpeedLockingTM performance for guaranteed ï¬xed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
â—† High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
â—† 32 to 512 macrocells; 32 to 768 registers
â—† 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
â—† Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
â—† Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-FriendlyTM inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
â—† Advanced E2CMOS process provides high-performance, cost-effective solutions
â—† Lead-free package options
Lead-
Free
Package
Options
Available!
Publication# ISPM4A Rev: M
Amendment/0
Issue Date: September 2006

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