IDT7188L Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
componentes Descripción
Fabricante
IDT7188L Datasheet PDF : 8 Pages
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IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
AC Electrical Characteristics (VCC = 5.0V ± 10%)
7188S25
7188L25
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time
25
____
35
—
45
—
55
____
70
____
85
____
ns
tAA Address Access Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
tACS Chip Select Access Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
tOH Output Hold from Address Change
5
____
5
____
5
____
5
____
5
____
5
____
ns
tLZ(1) Output Select to Output in Low-Z
5
____
5
____
5
____
5
____
5
____
5
____
ns
tHZ(1) Chip Deselect to Output in High-Z
____
10
____
14
____
14
____
20
____
25
____
30
ns
tPU(1) Chip Select to Power Up Time
0
____
0
____
0
____
0
____
0
____
0
____
ns
tPD(1) Chip Deselect to Power Down Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
NOTE:
1. This parameter is guaranteed by device characterization but is not production tested.
2989 tbl 11
Timing Waveform of Read Cycle No. 1(1,2)
tRC (5)
ADDRESS
DATAOUT
tAA
tOH
PREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 2(1,3)
tRC (5)
CS
DATAOUT
VCC SUPPLY ICC
CURRENT ISB
tACS
tLZ (4)
tPU
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state voltage.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
DATA VALID
,
2989 drw 06
tHZ (4)
DATA VALID
, HIGH IMPEDANCE
tPD
2989 drw 07
6.452
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