LC66558B Ver la hoja de datos (PDF) - SANYO -> Panasonic
Número de pieza
componentes Descripción
Fabricante
LC66558B
SANYO -> Panasonic
LC66558B Datasheet PDF : 22 Pages
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LC66556B, 66558B
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
Note
Maximum supply voltage
Input voltage
Output voltage
VDD max VDD
–0.3 to +7.0
V
VIN (1) P2, P3 (except for the P33/HOLD pin) and P6
–0.3 to +15.0
V
1
VIN (2) Other inputs
–0.3 to VDD + 0.3
V
2
P2, P3 (except for the P33/HOLD pin),
VOUT (1) P6, P7 and PA
–0.3 to +15.0
V
1
VOUT (2) Other outputs
–0.3 to VDD + 0.3
V
2
P0, P1, P2, P3 (except for the P33/HOLD pin),
ION (1) P4, P5, P6, P8, P9 and PC
4
mA
3
Output current per pin
ION (2)
–IOP (1)
–IOP (2)
P7, PA, PB
P0, P1, P4, P5, P7, PA, PB
P2, P3 (except for the P33/HOLD pin),
P6, P8, P9 and PC
20
mA
3
2
mA
4
4
mA
4
ΣION (1)
P2, P3 (except for the P33/HOLD pin),
P4, P5, P6, P7 and P8
75
mA
3
Total pin current
ΣION (2)
–ΣIOP (1)
P0, P1, P9, PA, PB, PC
P2, P3 (except for the P33/HOLD pin),
P4, P5, P6, P7 and P8
75
mA
3
25
mA
4
Allowable power dissipation
–ΣIOP (2) P0, P1, P9, PA, PB, PC
Pd max Ta = –30 to +70°C: DIP64S (QIP64E)
25
mA
4
600 (430)
mW
5
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Note: 1. Applies to open drain output specification pins. The rating from the “other pin” entry applies for specifications other than the open drain output
specification.
2. Levels up to the free-running oscillation level are allowed for the oscillator input and output pins.
3. Inflow current (For P8, the CMOS output specifications apply.)
4. Outflow current (Applies to pull-up output specification and CMOS output specification pins except P8.)
5. We recommend using reflow soldering methods to mount the QFP package version.
Contact your Sanyo sales representative to discuss process conditions if techniques in which the whole package is immersed in a solder bath
(solder dip or spray techniques) are used.
Allowable Operating Ranges at Ta = –30 to + 70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless specified otherwise
Parameter
Operating supply voltage
Memory retention supply voltage
Input high level Voltage
Intermediate level input voltage
Common-mode input voltage range
Low level input voltage
Operating frequency
(instruction cycle time)
Symbol
VDD
VDD (H)
VIH (1)
VIH (2)
VIH (3)
VIH (4)
VIM
VCMM (1)
VCMM (2)
VIL (1)
VIL (2)
VIL (3)
VIL (4)
Conditions
min
VDD
VDD: In hold mode
P2, P3 (except for the P33/HOLD pin), P6:
With the output n-channel transistor off
3.0
1.8
0.8 VDD
P33/HOLD, P9, RES, OSC1:
With the output n-channel transistor off
0.8 VDD
P0, P1, P4, P5, PC, PD, PE:
With the output n-channel transistor off
PE: When three-state input is used
PE: When three-state input is used
PD0, PC2: When comparator input is used
0.75
VDD
0.8 VDD
0.4 VDD
1.5
PD1, PD2, PD3, PC3: When comparator
input is used
VSS
P2, P3 (except for the P33/HOLD pin), P6, P9, RES,
OSC1:N-channel output, transistor off
VSS
P33/HOLD: VDD = 1.8 to 5.5 V
VSS
P0, P1, P4, P5, PC, PD, PE, TEST: N-channel output,
transistor off
VSS
PE: When three-state input is used
VSS
fop (TCYC)
0.4 (10)
typ
max
Unit
5.5 V
5.5 V
13.5 V
VDD
V
VDD
V
VDD
V
0.6 VDD
V
VDD
V
VDD –
1.5
V
0.2 VDD
0.2 VDD
0.25
VDD
0.2 VDD
4.35
(0.92)
V
V
V
V
MHz
(µs)
Note
1
2
3
2
3
Note: 1. Applies to open drain specification pins. However, the rating for VIH (2) applies to the P33/HOLD pin. Ports P2, P3 and P6 cannot be used as input
pins when CMOS output specifications are used.
2. Applies to open drain specification pins. P9, which has CMOS output specifications, can be used as input pins.
3. When PE is used as a three-value input, VIH (4), VIM and VIL (4) apply. Port PC cannot be used as input pins when CMOS output specifications
are used.
Continued on next page.
No. 5003-8/22
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