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LH28F160BG-TL

16 M-bit (1 MB x 16) Smart 3 Flash Memories

Sharp Electronics 

LH28F160BG-TL/BGH-TL

1 INTRODUCTION

This datasheet contains LH28F160BG-TL/BGH-TL A Command User Interface (CUI) serves as the

specifications. Section 1 provides a flash memory interface between the system processor and

overview. Sections 2, 3, 4 and 5 describe the internal operation of the device. A valid command

memory organization and functionality. Section 6 sequence written to the CUI initiates device

covers electrical specifications. LH28F160BG-TL/ automation. An internal Write State Machine (WSM)

BGH-TL flash memories documentation also automatically executes the algorithms and timings

includes ordering information which is referenced in necessary for block erase and word write

Section 7.

1.1 New Features

Key enhancements of LH28F160BG-TL/BGH-TL

Smart 3 flash memories are :

• 2.7 V VCC and VPP Write/Erase Operation

• Enhanced Suspend Capabilities

• Boot Block Architecture

Note following important differences :

• VPPLK has been lowered to 1.5 V to support

2.7 V block erase and word write operations.

operations.

A block erase operation erases one of the device’s

32 k-word blocks typically within 1.2 second (3.0 V

Y VCC and VPP), independent of other blocks. Each

block can be independently erased 100 000 times.

Block erase suspend mode allows system software

R to suspend block erase to read data from, or write

data to any other block.

A Writing memory data is performed in word

increments of the device’s 32 k-word blocks

N typically within 55 µs, 4 k-word blocks typically

Iwithin 60 µs (3.0 V VCC and VPP). Word write

Designs that switch VPP off during read

operations should make sure that the VPP

voltage transitions to GND.

M • To take advantage of Smart 3 technology, allow

I VPP connection to 2.7 V or 12 V.

L 1.2 Product Overview

The LH28F160BG-TL/BGH-TL are high-performance

16 M-bit Smart 3 flash memories organized as

E 1 024 k-word of 16 bits. The 1 024 k-word of data

is arranged in two 4 k-word boot blocks, six 4 k-

word parameter blocks and thirty-one 32 k-word

R main blocks which are individually erasable in-

P system. The memory map is shown in Fig. 1.

suspend mode enables the system to read data

from, or write data to any other flash memory array

location.

The boot block is located at either the top or the

bottom of the address map in order to

accommodate different micro-processor protect for

boot code location. The hardware-lockable boot

block provides complete code security for the

kernel code required for system initialization.

Locking and unlocking of the boot block is

controlled by WP# and/or RP# (see Section 4.9 for

details). Block erase or word write for boot block

must not be carried out by WP# to low and RP# to

VIH.

VPP at 2.7 V eliminates the need for a separate 12 V

converter, while VPP = 12 V maximizes block erase The status register indicates when the WSM’s block

and word write performance. In addition to flexible erase or word write operation is finished.

erase and program voltages, the dedicated VPP pin

gives complete data protection when VPP ≤ VPPLK.

The RY/BY# output gives an additional indicator of

WSM activity by providing both a hardware signal

-5-

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