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74HC4515 Datasheet PDF : 9 Pages
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Philips Semiconductors
4-to-16 line decoder/demultiplexer with
input latches; inverting
Product specification
74HC/HCT4515
FEATURES
• Inverting outputs
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4515 are high-speed Si-gate CMOS
devices and are pin compatible with “4515” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4515 are 4-to-16 line
decoders/demultiplexers having four binary weighted
address inputs (A0 to A3) with latches, a latch enable input
(LE), and an active LOW enable input (E). The 16 inverting
outputs (Q0 to Q15) are mutually exclusive active LOW.
When LE is HIGH, the selected output is determined by the
data on An. When LE goes LOW, the last data present at
An are stored in the latches and the outputs remain stable.
When E is LOW, the selected output, determined by the
contents of the latch, is LOW. When E is HIGH, all outputs
are HIGH. The enable input (E) does not affect the state of
the latch.
When the “4515” is used as a demultiplexer, E is the data
input and A0 to A3 are the address inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL PARAMETER
CONDITIONS
tPHL/ tPLH
CI
CPD
propagation delay An to Qn
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
TYPICAL
HC
HCT
25
26
3.5
3.5
44
46
UNIT
ns
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2
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