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74HC4515
(Rev.:2018)

4-to-16 line decoder/demultiplexer with input latches; inverting

NXP Semiconductors. 

Nexperia

74HC4515

4-to-16 line decoder/demultiplexer with input latches; inverting

6 Pinning information

6.1 Pinning

LE 1

A0 2

A1 3

Q7 4

Q6 5

Q5 6

Q4 7

Q3 8

Q1 9

Q2 10

Q0 11

GND 12

Figure 5. Pin configuration for SO24 (SOT137-1)

74HC4515

24 VCC

23 E

22 A3

21 A2

20 Q10

19 Q11

18 Q8

17 Q9

16 Q14

15 Q15

14 Q12

13 Q13

aaa-028697

6.2 Pin description

Table 2. Pin description

Symbol

LE

E

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,

Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15

A0, A1, A2, A3

GND

VCC

Pin

1

23

11, 9, 10, 8, 7, 6, 5, 4,

18, 17, 20, 19, 14, 13, 16, 15

2, 3, 21, 22

12

24

Description

latch enable input (active HIGH)

enable input (active LOW)

multiplexer outputs (active LOW)

address inputs

ground (0 V)

supply voltage

74HC4515

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 2 July 2018

© Nexperia B.V. 2018. All rights reserved.

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