DAC08
10kΩ
15V
2
10V
VO
6
REF01* 5
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
5.000kΩ
IO
4
5.0kΩ
2
V+ –V CC VLC IO
4
*OR ADR01
+15V –15V
5.0kΩ
+15V
AD8671
B1 B2 B3 B4 B5 B6 B7 B8 EO
POS. FULL RANGE
EO ZERO SCALE
1 1 1 1 1 1 1 1 +4.960
1 0 0 0 1 0 0 0 0.000
NEG. FULL SCALE +1LSB 0 0 0 0 0 0 0 1 –4.960
NEG. FULL SCALE
0 0 0 0 0 0 0 0 –5.000
–15V
Figure 29. Offset Binary Operation
RL
IO
4
2
IO
AD8671
EO
0 TO –IFR × RL
255
IFR = 256 IREF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT INVERTING INPUT OF OP AMP TO IO (PIN 2): CONNECT IO (PIN 4)
TO GROUND.
Figure 30. Positive Low Impedance Output Operation
4
IO
AD8671
EO
2
IO
RL
0 TO –IFR × RL
255
IFR = 256 IREF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT NONINVERTING INPUT OF OP AMP TO IO (PIN 2): CONNECT IO (PIN 4)
TO GROUND.
Figure 31. Negative Low Impedance Output Operation
TTL, DTL,
VTH = 1.4V
VLC
1
VTH = VLC 1.4V
15V CMOS
15V VTH = 7.6V
ECL
CMOS, HTL, NMOS
V+
9.1kΩ
6.2kΩ
VLC
0.1µF
13kΩ
20kΩ
2N3904
"A"
3kΩ
39kΩ
2N3904
TO PIN 1
VLC
6.2kΩ
2N3904
"A"
3kΩ
20kΩ
2N3904
TO PIN 1
VLC
R3
400µA
–5.2V
TEMPERATURE COMPENSATING VLC CIRCUITS
Figure 32. Interfacing with Various Logic Families
Rev. C | Page 12 of 20