SPT7725 Ver la hoja de datos (PDF) - Signal Processing Technologies
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SPT7725 Datasheet PDF : 12 Pages
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Table I - Output Coding
ANALOG INPUT VOLTAGE D8
-2 V + 1/2 LSB
0
-1.0 V
0
0 V - 1/2 LSB
0
≥0 V
1
BINARY
TRUE
INVERTED
MINV=LINV=0 MINV=LINV=1
D7 _____ D0
00000000
D7 ______ D0
11111111
00000001
11111110
01111111
10000000
10000000
01111111
11111111
00000000
11111110
00000001
11111111
00000000
TWOs COMPLEMENT
TRUE
INVERTED
MINV=1; LINV=0 MINV=0; LINV=1
D7 ______ D0
10000000
D7 ______ D0
01111111
10000001
01111110
11111111
00000000
00000000
11111111
01111111
10000000
01111110
10000001
01111111
10000000
D0 TO D7 (DIGITAL OUTPUTS)
The digital outputs can drive ECL levels into 50 Ω when
pulled down to -2 V. When pulled down to -5.2 V, the outputs
can drive 150 Ω to 1 kΩ loads.
VRBF, VR2, VRTF (REFERENCE INPUTS)
There are two reference inputs and one external reference
voltage tap. These are -2 V (VRBF), mid-tap (VR2) and AGND
(VRTF). The reference pins can be driven as shown in
figure 1. VR2 should be bypassed to AGND for further noise
suppression.
minimum setup and hold times. DRINV is a data ready
inverse control pin. (See the timing diagram.)
D8 - OVERRANGE (PGA AND CERQUAD PACKAGES
ONLY)
This is an overrange function. When the SPT7725 is in an
overrange condition, D8 goes high and all data outputs go
high as well. This makes it possible to include the SPT7725
into higher resolution systems.
OPERATION
VRBF, VRBS, VR1, VR2, VR3, VRTF, VRTS REFERENCE
INPUTS (PGA AND CERQUAD PACKAGES ONLY)
These are five external reference voltage taps from -2 V
(VRBF) to AGND (VRTF) which can be used to control integral
linearity over temperature. The taps can be driven by op
amps as shown in figure 2. These voltage level inputs can be
bypassed to AGND for further noise suppression if so de-
sired. VRB and VRT have force and sense pins for monitoring
the top and bottom voltage references.
N/C
All Not Connected pins should be tied to DGND on the left
side of the package and to AGND on the right side of the
package.
DREAD - DATA READY, DRINV - DATA READY INVERSE
(PGA AND CERQUAD PACKAGES ONLY)
The data ready pin is a flag that goes high or low at the output
when data is valid or ready to be received. It is essentially a
delay line that accounts for the time necessary for information
to be clocked through the SPT7725's decoders and latches.
This function is useful for interfacing with high speed memory.
Using the data ready output to latch the output data ensures
The SPT7725 has 256 preamp/comparator pairs which are
each supplied with the voltage from VRTF to VRBF divided
equally by the resistive ladder as shown in the block diagram.
This voltage is applied to the positive input of each preampli-
fier/comparator pair. An analog input voltage applied at VIN
is connected to the negative inputs of each preamplifier/
comparator pair. The comparators are then clocked through
each comparator's individual clock buffer. When CLK is in
the low state, the master or input stage of the comparators
compares the analog input voltage to the respective refer-
ence voltage. When CLK changes from low to high, the
comparators are latched to the state prior to the clock
transition and output logic codes in sequence from the top
comparators, closest to VRTF (0 V), down to the point where
the magnitude of the input signal changes sign (thermometer
code). The output of each comparator is then registered into
four 64-to-6 bit decoders when CLK is changes from high to
low. At the output of the decoders is a set of four 7-bit latches
which are enabled (track) when CLK changes from high to
low. From here, the outputs of the latches are coded into
6 LSBs from 4 columns and 4 columns are coded into
2 MSBs. Next are the MINV and LINV controls for output
inversions which consist of a set of eight XOR gates. Finally,
8 ECL output latches and buffers are used to drive the
external loads. The conversion takes one clock cycle from
the input to the data outputs.
SPT
7
SPT7725
12/30/98
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