HM658512A Ver la hoja de datos (PDF) - Hitachi -> Renesas Electronics
Número de pieza
componentes Descripción
Fabricante
HM658512A Datasheet PDF : 22 Pages
| |||
HM658512A Series
At the end of self refresh, refresh reset time (tRFS) is required to reset the internal self refresh operation of
the RAM. During tRFS, CE and OE/RFSH must be kept high. If auto refresh follows self refresh, low
transition of OE/RFSH at the beginning of automatic refresh must not occur during tRFS period.
Notes on Using the HM658512A
Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive
than conventional SRAM’s.
(1) If a short CE pulse of a width less than tCE min is applied to RAM, an incomplete read occurs and
stored data may be destroyed. Make sure that CE low pulses of less than tCE min are inhibited. Note
that a 10 ns CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is
generated by the decoding of higher address signals on the board. Avoid these short pulses.
(2) OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an
incomplete refresh that will destroy data. Make sure that OE/RFSH low pulse of less than tFAP min are
also inhibited.
(3) tOHC and tOCD are the timing specs which distinguish the OE function of OE/RFSH from the RFSH
function. The tOHC and tOCD specs must be strictly maintained.
(4) Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100
µs after the power voltage reaches 4.5 V-5.5 V after power-on.
Function Table
CE
OE/RFSH
WE
L
L
H
L
X
L
L
H
H
H
L
X
H
H
X
Note: X means H or L.
I/O pin
Dout
High-Z
High-Z
High-Z
High-Z
Mode
Read
Write
—
Refresh
Standby
7
Share Link: 