KSZ8051MNL Ver la hoja de datos (PDF) - Microchip Technology
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KSZ8051MNL Datasheet PDF : 66 Pages
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KSZ8051MNL/RNL
3.2.1.6 Receive Data[3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
3.2.1.7 Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY
can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being
transferred from the PHY.
RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
3.2.1.8 Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
• In 10 Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
• In 100 Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is de-
asserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts
CRS if IDLE symbols are received without /T/R.
3.2.1.9 Collision Detection (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
3.2.2 MII SIGNAL DIAGRAM
The KSZ8051MNL MII pin connections to the MAC are shown in Figure 3-2.
FIGURE 3-2:
KSZ8051MNL MII INTERFACE
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KSZ8051MNL
TXC
TXEN
TXD[3:0]
MII
Ethernet MAC
TXC
TXEN
TXD[3:0]
RXC
RXDV
RXD[3:0]
RXER
CRS
COL
RXC
RXDV
RXD[3:0]
RXER
CRS
COL
2016 Microchip Technology Inc.
DS00002310A-page 19
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