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KSZ8051MNL Datasheet PDF : 66 Pages
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KSZ8051MNL/RNL
Note 2-2
Note 2-3
RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the
MAC.
RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7 kΩ) or pull-downs (1.0 kΩ) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
TABLE 2-4:
Pin Number
15
14
13
18
29
28
20
31
16
30
19
STRAP-IN OPTIONS - KSZ8051RNL
Pin Name
Type
Note 2-4
Description
PHYAD2
PHYAD1
PHYAD0
CONFIG2
Ipd/O
Ipd/O
Ipu/O
PHYAD[2:0] is latched at de-assertion of reset and is configurable to
any value from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY
address, but it can be assigned as a unique PHY address after pull-
ing the B-CAST_OFF strapping pin high or writing a ‘1’ to Register
16h, bit [9].
PHY Address bits [4:3] are set to 00 by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of
reset.
CONFIG1
CONFIG0
ISO
SPEED
DUPLEX
NWAYEN
B-CAST_OFF
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipd/O
CONFIG[2:0] Mode
000
RMII (default)
110
RMII back-to-back
001 – 101,
111
Reserved, not used
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [10].
Speed mode
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
At the de-assertion of reset, this pin value is latched into Register 0h,
bit [13] as the speed select, and also is latched into Register 4h
(auto-negotiation advertisement) as the speed capability support.
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [8].
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [12].
Broadcast Off – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY
address
At the de-assertion of reset, this pin value is latched by the chip.
2016 Microchip Technology Inc.
DS00002310A-page 13
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