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SDA30C163-2

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SDA 30C163-2

2 Functional Description

2.1 Architecture

The CPU manipulates operands in three memory spaces. These are the program memory

(512 Kbyte) and (256 + 1024) byte internal data memory spaces. The program memory address

space is provided to accommodate relocatable code.

The internal data memory address space is further divided into the 256-byte internal data RAM,

1024 bytes XRAM and the 128-byte Special Function Register (SFR) address spaces. Four register

banks (each bank has eight registers),128 addressable bits, and the stack reside in the internal data

RAM. The stack depth is limited only by the available internal data RAM. Its location is determined

by the 8-bit stack pointer. All registers except the program counter and the four 8-register banks

reside in the special function register address space. These memory mapped registers include

arithmetic registers, pointers, I/O-ports, registers for the interrupt system, timers, pulse width

modulator and serial channel. Many locations in the SFR-address space are addressable as bits.

Note that reading from unused locations in internal data memory will yield undefined data.

Conditional branches are performed relative to the program counter. The register-indirect jump

permits branching relative to a 16-bit base register with an offset provided by an 8-bit index register.

Sixteen-bit jumps and calls permit branching to any location within one 64 K block of the 512 K

program memory address space.

There are five methods for addressing source operands: register, direct, register-indirect,

immediate, and base-register plus index-register indirect addressing.

The first three methods can be used for addressing destination operands. Most instructions have a

“destination, source” field that specifies the data type, addressing methods and operands involved.

For operations other than moves, the destination operand is also a source operand.

Registers in the four 8-register banks can be accessed through register, direct, or register-indirect

addressing; the lower 128 bytes of internal data RAM through direct or register-indirect addressing,

the upper 128 bytes of internal data RAM through register-indirect addressing; and the special

function registers through direct addressing. Look-up tables resident in program memory can be

accessed through base-register plus index-register indirect addressing.

2.1.1 CPU-Hardware

Instruction Decoder

Each program instruction is decoded by the instruction decoder. This unit generates the internal

signals that control the functions of each unit within the CPU-section. These signals control the

sources and destination of data, as well as the function of the Arithmetic/Logic Unit (ALU).

Program Control Section

The program control section controls the sequence in which the instructions stored in program

memory are executed. The conditional branch logic enables conditions internal and external to the

processor to cause a change in the sequence of program execution. The 16-bit program counter

holds the address of the instruction to be executed. It is manipulated with the control transfer

instructions listed in chapter “Instruction Set”.

Semiconductor Group

13

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